URL https://opencores.org/ocsvn/uart8systemc/uart8systemc/trunk

Subversion Repositories uart8systemc

[/] [uart8systemc/] [trunk/] [testbench/] [module_tb.v] - Diff between revs 2 and 7

Rev 2	Rev 7
Line 1...	Line 1...

`timescale 1ns/1ns	`timescale 1ns/1ns
`module module_tb;`	`module module_tb;`

`reg CLK;`	`reg CLK;`

`wire RESET;`	`wire RESET;`
`wire RX;`	`wire RX;`
`wire START;`	`wire START;`
`wire [7:0] DATA_TX;`	`wire [7:0] DATA_TX;`
`wire [11:0] WORK_FR;`	`wire [11:0] WORK_FR;`
Line 12...	Line 13...
`wire [7:0] DATA_RX;`	`wire [7:0] DATA_RX;`
`wire PARITY_RX;`	`wire PARITY_RX;`
`wire READY_TX;`	`wire READY_TX;`
`wire READY;`	`wire READY;`

`assign DATA_TX = DATA_RX;`

`initial CLK = 1'b0;`
`always #(10) CLK = ~CLK;`

`integer i;`	`integer i;`
	`integer a;`
	`//assign DATA_TX = DATA_RX;`

`initial`	`initial`
`begin`	`begin`
`$dumpfile("module_tb.vcd");`	`$dumpfile("module_tb.vcd");`
`$dumpvars(0,module_tb);`	`$dumpvars(0,module_tb);`
`$global_init;`	`$global_init;`
`i=0;`	`i=0;`
	`a=10;`
`end`	`end`

	`initial CLK = 1'b0;`
	`always #(a) CLK = ~CLK;`

`UART DUT(`	`UART DUT(`
`.CLK(CLK),`	`.CLK(CLK),`
`.RESET(RESET),`	`.RESET(RESET),`
`.RX(RX),`	`.RX(RX),`
`.START(START),`	`.START(START),`
Line 46...	Line 48...

`always@(posedge CLK)`	`always@(posedge CLK)`
`$reset_uart;`	`$reset_uart;`

`always@(posedge CLK)`	`always@(posedge CLK)`
`$execute_uart;`	`$run_sim;`

`always@(posedge CLK)`
`$global_counter;`

`//FLAG USED TO FINISH SIMULATION PROGRAM`	`//FLAG USED TO FINISH SIMULATION PROGRAM`
`always@(posedge CLK)`	`always@(posedge CLK)`
`begin`	`begin`
`wait(i == 1);`	`wait(i == 1);`