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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_communication_block.vhd] - Diff between revs 12 and 32

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Rev 12 Rev 32
Line 41... Line 41... 
   signal data_sent_tx : std_logic;
 
   signal data_sent_tx : std_logic;
 
   signal data_received_rx : std_logic;
 
   signal data_received_rx : std_logic;
 
   signal serial_out : std_logic;
 
   signal serial_out : std_logic;
 
 
 
 
 
   -- Clock period definitions   
   -- Clock period definitions   
        constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
 
        constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
 
 
 
 
 
BEGIN
 
BEGIN
 
 
 
 
 
        -- Instantiate the Unit Under Test (UUT)
 
        -- Instantiate the Unit Under Test (UUT)
 
   uut: uart_communication_blocks PORT MAP (
 
   uut: uart_communication_blocks PORT MAP (
Line 75... Line 75... 
   stim_proc: process
 
   stim_proc: process
 
   begin
 
   begin
 
      -- Setup communication blocks
 
      -- Setup communication blocks
 
                rst <= '1';
 
                rst <= '1';
 
                serial_in <= '1'; -- Idle..
 
                serial_in <= '1'; -- Idle..
 
                cycle_wait_baud <= conv_std_logic_vector(16, (nBitsLarge));
 
                cycle_wait_baud <= conv_std_logic_vector(434, (nBitsLarge));
 
                start_tx <= '0';
 
                start_tx <= '0';
 
      wait for 2 ns;
 
      wait for 2 ns;
 
                rst <= '0';
 
                rst <= '0';
 
 
 
 
 
                -- Send data..
 
                -- Send data..
Line 121... Line 121... 
                serial_in <= '0';
 
                serial_in <= '0';
 
      wait for 8.68 us;
 
      wait for 8.68 us;
 
 
 
 
 
                -- Stop bit here
 
                -- Stop bit here
 
                serial_in <= '1';
 
                serial_in <= '1';
 
                wait for clk_period*20;
 
                wait for clk_period*200;
 
 
 
 
 
                -- Receive 0xC4 value (11000100)
 
                -- Receive 0xC4 value (11000100)
 
                serial_in <= '0'; -- Start bit
 
                serial_in <= '0'; -- Start bit
 
                wait for 8.68 us;
 
                wait for 8.68 us;
 
 
 
 
Line 146... Line 146... 
                serial_in <= '1';
 
                serial_in <= '1';
 
      wait for 8.68 us;
 
      wait for 8.68 us;
 
 
 
 
 
                -- Stop bit here
 
                -- Stop bit here
 
                serial_in <= '1';
 
                serial_in <= '1';
 
                wait for clk_period*20;
 
                wait for clk_period*200;
 
 
 
 
 
 
 
 
 
 
 
 
 
      -- Stop Simulation
 
      -- Stop Simulation
 
                assert false report "NONE. End of simulation." severity failure;
 
                assert false report "NONE. End of simulation." severity failure;

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