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[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [testUart_wishbone_slave.vhd] - Diff between revs 20 and 21
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| Rev 20 |
Rev 21 |
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DAT_O0 : OUT std_logic_vector(31 downto 0);
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DAT_O0 : OUT std_logic_vector(31 downto 0);
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WE_I : IN std_logic;
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WE_I : IN std_logic;
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STB_I : IN std_logic;
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STB_I : IN std_logic;
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ACK_O : OUT std_logic;
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ACK_O : OUT std_logic;
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serial_in : IN std_logic;
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serial_in : IN std_logic;
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data_Avaible : out std_logic; -- Indicate that the receiver module got something
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serial_out : OUT std_logic
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serial_out : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Outputs
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--Outputs
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signal DAT_O0 : std_logic_vector(31 downto 0);
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signal DAT_O0 : std_logic_vector(31 downto 0);
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signal ACK_O : std_logic;
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signal ACK_O : std_logic;
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signal serial_out : std_logic;
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signal serial_out : std_logic;
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signal data_Avaible : std_logic;
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-- Clock period definitions (1.8432MHz)
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-- Clock period definitions (1.8432MHz)
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constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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constant CLK_I_period : time := 20 ns; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
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BEGIN
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BEGIN
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DAT_O0 => DAT_O0,
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DAT_O0 => DAT_O0,
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WE_I => WE_I,
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WE_I => WE_I,
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STB_I => STB_I,
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STB_I => STB_I,
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ACK_O => ACK_O,
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ACK_O => ACK_O,
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serial_in => serial_in,
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serial_in => serial_in,
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data_Avaible => data_Avaible,
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serial_out => serial_out
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serial_out => serial_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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CLK_I_process :process
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CLK_I_process :process
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