--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 09:35:58 06/03/2011
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-- Create Date: 09:35:58 06/03/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
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-- Module Name: C:/Users/pjf/Documents/projects/fpga/xilinx/Network/ip1/IPv4_TX_tb.vhd
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-- Project Name: ip1
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-- Project Name: ip1
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-- Target Device:
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-- Target Device:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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--
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--
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-- VHDL Test Bench Created by ISE for module: IPv4_TX
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-- VHDL Test Bench Created by ISE for module: IPv4_TX
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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-- simulation model.
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.axi.all;
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use work.axi.all;
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use work.ipv4_types.all;
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use work.ipv4_types.all;
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use work.arp_types.all;
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use work.arp_types.all;
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ENTITY IPv4_TX_tb IS
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ENTITY IPv4_TX_tb IS
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END IPv4_TX_tb;
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END IPv4_TX_tb;
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ARCHITECTURE behavior OF IPv4_TX_tb IS
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ARCHITECTURE behavior OF IPv4_TX_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT IPv4_TX
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COMPONENT IPv4_TX
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PORT(
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PORT(
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-- IP Layer signals
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-- IP Layer signals
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ip_tx_start : in std_logic;
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ip_tx_start : in std_logic;
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ip_tx : in ipv4_tx_type; -- IP tx cxns
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ip_tx : in ipv4_tx_type; -- IP tx cxns
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ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
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ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
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ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
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ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
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|
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-- system signals
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-- system signals
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clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
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clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
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reset : in STD_LOGIC;
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reset : in STD_LOGIC;
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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our_mac_address : in std_logic_vector (47 downto 0);
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-- ARP lookup signals
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-- ARP lookup signals
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arp_req_req : out arp_req_req_type;
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arp_req_req : out arp_req_req_type;
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arp_req_rslt : in arp_req_rslt_type;
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arp_req_rslt : in arp_req_rslt_type;
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-- MAC layer TX signals
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-- MAC layer TX signals
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mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
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mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
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mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
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mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
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mac_data_out_ready : in std_logic; -- indicates system ready to consume data
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mac_data_out_ready : in std_logic; -- indicates system ready to consume data
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mac_data_out_valid : out std_logic; -- indicates data out is valid
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mac_data_out_valid : out std_logic; -- indicates data out is valid
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mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
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mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
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mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
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mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
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mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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signal ip_tx_start : std_logic := '0';
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signal ip_tx_start : std_logic := '0';
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signal ip_tx : ipv4_tx_type;
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signal ip_tx : ipv4_tx_type;
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signal clk : std_logic := '0';
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signal clk : std_logic := '0';
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signal reset : std_logic := '0';
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signal reset : std_logic := '0';
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signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
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signal our_ip_address : std_logic_vector(31 downto 0) := (others => '0');
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signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
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signal our_mac_address : std_logic_vector(47 downto 0) := (others => '0');
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signal mac_tx_granted : std_logic := '0';
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signal mac_tx_granted : std_logic := '0';
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signal mac_data_out_ready : std_logic := '0';
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signal mac_data_out_ready : std_logic := '0';
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signal arp_req_rslt : arp_req_rslt_type;
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signal arp_req_rslt : arp_req_rslt_type;
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--Outputs
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--Outputs
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signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
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signal ip_tx_result : std_logic_vector (1 downto 0); -- tx status (changes during transmission)
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signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
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signal ip_tx_data_out_ready : std_logic; -- indicates IP TX is ready to take data
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signal mac_tx_req : std_logic;
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signal mac_tx_req : std_logic;
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signal mac_data_out_valid : std_logic;
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signal mac_data_out_valid : std_logic;
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signal mac_data_out_last : std_logic;
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signal mac_data_out_last : std_logic;
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signal mac_data_out_first : std_logic;
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signal mac_data_out : std_logic_vector(7 downto 0);
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signal mac_data_out : std_logic_vector(7 downto 0);
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signal arp_req_req : arp_req_req_type;
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signal arp_req_req : arp_req_req_type;
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-- Clock period definitions
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-- Clock period definitions
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constant clk_period : time := 8 ns;
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constant clk_period : time := 8 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: IPv4_TX PORT MAP (
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uut: IPv4_TX PORT MAP (
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ip_tx_start => ip_tx_start,
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ip_tx_start => ip_tx_start,
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ip_tx => ip_tx,
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ip_tx => ip_tx,
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ip_tx_result => ip_tx_result,
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ip_tx_result => ip_tx_result,
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ip_tx_data_out_ready => ip_tx_data_out_ready,
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ip_tx_data_out_ready => ip_tx_data_out_ready,
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clk => clk,
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clk => clk,
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reset => reset,
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reset => reset,
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our_ip_address => our_ip_address,
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our_ip_address => our_ip_address,
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our_mac_address => our_mac_address,
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our_mac_address => our_mac_address,
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arp_req_req => arp_req_req,
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arp_req_req => arp_req_req,
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arp_req_rslt => arp_req_rslt,
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arp_req_rslt => arp_req_rslt,
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mac_tx_req => mac_tx_req,
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mac_tx_req => mac_tx_req,
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mac_tx_granted => mac_tx_granted,
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mac_tx_granted => mac_tx_granted,
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mac_data_out_ready => mac_data_out_ready,
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mac_data_out_ready => mac_data_out_ready,
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mac_data_out_valid => mac_data_out_valid,
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mac_data_out_valid => mac_data_out_valid,
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mac_data_out_first => mac_data_out_first,
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mac_data_out_last => mac_data_out_last,
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mac_data_out_last => mac_data_out_last,
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mac_data_out => mac_data_out
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mac_data_out => mac_data_out
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clk_process :process
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clk_process :process
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begin
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begin
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clk <= '0';
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clk <= '0';
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wait for clk_period/2;
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wait for clk_period/2;
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clk <= '1';
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clk <= '1';
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wait for clk_period/2;
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wait for clk_period/2;
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end process;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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our_ip_address <= x"c0a80509"; -- 192.168.5.9
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our_ip_address <= x"c0a80509"; -- 192.168.5.9
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our_mac_address <= x"002320212223";
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our_mac_address <= x"002320212223";
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ip_tx_start <= '0';
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ip_tx_start <= '0';
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mac_tx_granted <= '0';
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mac_tx_granted <= '0';
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mac_data_out_ready <= '0';
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mac_data_out_ready <= '0';
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out_last <= '0';
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ip_tx.data.data_out_last <= '0';
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arp_req_rslt.got_mac <= '0';
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arp_req_rslt.got_err <= '0';
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arp_req_rslt.mac <= (others => '0');
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reset <= '1';
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reset <= '1';
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wait for clk_period*10;
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wait for clk_period*10;
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reset <= '0';
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reset <= '0';
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wait for clk_period*5;
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wait for clk_period*5;
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-- check reset conditions
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-- check reset conditions
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assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
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assert arp_req_req.lookup_req = '0' report "arp_req_req.lookup_req not initialised correctly on reset";
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assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
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assert ip_tx_result = IPTX_RESULT_NONE report "ip_tx_result not initialised correctly on reset";
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assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
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assert ip_tx_data_out_ready = '0' report "ip_tx_data_out_ready not initialised correctly on reset";
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assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
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assert mac_tx_req = '0' report "mac_tx_req not initialised correctly on reset";
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assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
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assert mac_data_out_valid = '0' report "mac_data_out_valid not initialised correctly on reset";
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assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
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assert mac_data_out_last = '0' report "mac_data_out_last not initialised correctly on reset";
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-- insert stimulus here
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-- insert stimulus here
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------------
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------------
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-- TEST 1 -- basic functional tx test with some delays for arp and chn access
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-- TEST 1 -- basic functional tx test with some delays for arp and chn access
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------------
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------------
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report "T1: basic functional tx test with some delays for arp and chn access";
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report "T1: basic functional tx test with some delays for arp and chn access";
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ip_tx.hdr.protocol <= x"35";
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ip_tx.hdr.protocol <= x"35";
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ip_tx.hdr.data_length <= x"0008";
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ip_tx.hdr.data_length <= x"0008";
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ip_tx.hdr.dst_ip_addr <= x"c0123478";
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ip_tx.hdr.dst_ip_addr <= x"c0123478";
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ip_tx_start <= '1';
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ip_tx_start <= '1';
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wait for clk_period;
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wait for clk_period;
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ip_tx_start <= '0'; wait for clk_period;
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ip_tx_start <= '0'; wait for clk_period;
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arp_req_rslt.got_mac <= '0';
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arp_req_rslt.got_mac <= '0';
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arp_req_rslt.got_err <= '0';
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assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
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assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
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assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
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assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
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wait for clk_period*10; -- simulate arp lookup time
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wait for clk_period*10; -- simulate arp lookup time
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arp_req_rslt.mac <= x"050423271016";
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arp_req_rslt.mac <= x"050423271016";
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arp_req_rslt.got_mac <= '1';
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arp_req_rslt.got_mac <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
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assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
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assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
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assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
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wait for clk_period*10; -- simulate mac chn access time
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wait for clk_period*10; -- simulate mac chn access time
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mac_tx_granted <= '1';
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mac_tx_granted <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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mac_data_out_ready <= '1';
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mac_data_out_ready <= '1';
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assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
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assert mac_data_out_valid = '0' report "T1: mac_data_out_valid asserted too early";
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wait for clk_period;
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wait for clk_period;
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assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
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assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
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wait for clk_period;
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wait for clk_period;
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assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
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assert mac_data_out_valid = '1' report "T1: mac_data_out_valid not asserted";
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-- wait until in eth hdr
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-- wait until in eth hdr
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wait for clk_period*3;
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wait for clk_period*3;
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-- go mac not ready for 2 clocks
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-- go mac not ready for 2 clocks
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mac_data_out_ready <= '0';
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mac_data_out_ready <= '0';
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wait for clk_period*2;
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wait for clk_period*2;
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mac_data_out_ready <= '1';
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mac_data_out_ready <= '1';
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wait until ip_tx_data_out_ready = '1';
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wait until ip_tx_data_out_ready = '1';
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-- start to tx IP data
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-- start to tx IP data
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ip_tx.data.data_out_valid <= '1';
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ip_tx.data.data_out_valid <= '1';
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ip_tx.data.data_out <= x"56"; wait for clk_period;
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ip_tx.data.data_out <= x"56"; wait for clk_period;
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-- delay data in for 1 clk cycle
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-- delay data in for 1 clk cycle
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out <= x"57"; wait for clk_period;
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ip_tx.data.data_out <= x"57"; wait for clk_period;
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ip_tx.data.data_out_valid <= '1'; wait for clk_period;
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ip_tx.data.data_out_valid <= '1'; wait for clk_period;
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ip_tx.data.data_out <= x"58"; wait for clk_period;
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ip_tx.data.data_out <= x"58"; wait for clk_period;
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ip_tx.data.data_out <= x"59"; wait for clk_period;
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ip_tx.data.data_out <= x"59"; wait for clk_period;
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|
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-- delay mac ready for 2 clk cycles
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-- delay mac ready for 2 clk cycles
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mac_data_out_ready <= '0';
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mac_data_out_ready <= '0';
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ip_tx.data.data_out <= x"5a"; wait for clk_period;
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ip_tx.data.data_out <= x"5a"; wait for clk_period;
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assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
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assert ip_tx_data_out_ready = '0' report "T1: ip_tx_data_out_ready not cleared when mac not ready";
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|
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ip_tx.data.data_out <= x"5a"; wait for clk_period;
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ip_tx.data.data_out <= x"5a"; wait for clk_period;
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mac_data_out_ready <= '1';
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mac_data_out_ready <= '1';
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wait until ip_tx_data_out_ready = '1';
|
wait until ip_tx_data_out_ready = '1';
|
wait for clk_period;
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wait for clk_period;
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assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
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assert ip_tx_data_out_ready = '1' report "T1: ip_tx_data_out_ready not set when mac ready";
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ip_tx.data.data_out <= x"5b"; wait for clk_period;
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ip_tx.data.data_out <= x"5b"; wait for clk_period;
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ip_tx.data.data_out <= x"5c"; wait for clk_period;
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ip_tx.data.data_out <= x"5c"; wait for clk_period;
|
|
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ip_tx.data.data_out <= x"5d";
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ip_tx.data.data_out <= x"5d";
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ip_tx.data.data_out_last <= '1';
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ip_tx.data.data_out_last <= '1';
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wait for clk_period;
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wait for clk_period;
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assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
|
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
|
|
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out_valid <= '0';
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ip_tx.data.data_out_last <= '0';
|
ip_tx.data.data_out_last <= '0';
|
wait for clk_period*2;
|
wait for clk_period*2;
|
|
|
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
|
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
|
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
|
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
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|
|
mac_tx_granted <= '0';
|
mac_tx_granted <= '0';
|
wait for clk_period*2;
|
wait for clk_period*2;
|
|
|
------------
|
------------
|
-- TEST 2 -- basic functional tx test with no delays for arp and chn access
|
-- TEST 2 -- basic functional tx test with no delays for arp and chn access
|
------------
|
------------
|
|
|
report "T2: basic functional tx test with no delays for arp and chn access";
|
report "T2: basic functional tx test with no delays for arp and chn access";
|
|
|
ip_tx.hdr.protocol <= x"11";
|
ip_tx.hdr.protocol <= x"11";
|
ip_tx.hdr.data_length <= x"0006";
|
ip_tx.hdr.data_length <= x"0006";
|
ip_tx.hdr.dst_ip_addr <= x"c0123478";
|
ip_tx.hdr.dst_ip_addr <= x"c0123478";
|
ip_tx_start <= '1';
|
ip_tx_start <= '1';
|
wait for clk_period;
|
wait for clk_period;
|
ip_tx_start <= '0'; wait for clk_period;
|
ip_tx_start <= '0'; wait for clk_period;
|
arp_req_rslt.got_mac <= '0';
|
arp_req_rslt.got_mac <= '0';
|
|
|
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
|
assert arp_req_req.lookup_req = '1' report "T1: lookup_req not set on tx start";
|
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
|
assert ip_tx_result = IPTX_RESULT_SENDING report "T1: result should be IPTX_RESULT_SENDING";
|
|
|
wait for clk_period; -- simulate arp lookup time
|
wait for clk_period; -- simulate arp lookup time
|
arp_req_rslt.mac <= x"050423271016";
|
arp_req_rslt.mac <= x"050423271016";
|
arp_req_rslt.got_mac <= '1';
|
arp_req_rslt.got_mac <= '1';
|
|
|
wait for clk_period*2;
|
wait for clk_period*2;
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|
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assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
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assert arp_req_req.lookup_req = '0' report "T1: lookup_req not clear after setting";
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assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
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assert mac_tx_req = '1' report "T1: mac_tx_req not set after getting mac";
|
|
|
wait for clk_period; -- simulate mac chn access time
|
wait for clk_period; -- simulate mac chn access time
|
mac_tx_granted <= '1';
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mac_tx_granted <= '1';
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wait for clk_period*2;
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wait for clk_period*2;
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mac_data_out_ready <= '1';
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mac_data_out_ready <= '1';
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|
|
assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
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assert ip_tx_data_out_ready = '0' report "T1: IP data out ready asserted too early";
|
|
|
wait until ip_tx_data_out_ready = '1';
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wait until ip_tx_data_out_ready = '1';
|
|
|
-- start to tx IP data
|
-- start to tx IP data
|
ip_tx.data.data_out_valid <= '1';
|
ip_tx.data.data_out_valid <= '1';
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ip_tx.data.data_out <= x"c1"; wait for clk_period;
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ip_tx.data.data_out <= x"c1"; wait for clk_period;
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ip_tx.data.data_out <= x"c2"; wait for clk_period;
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ip_tx.data.data_out <= x"c2"; wait for clk_period;
|
ip_tx.data.data_out <= x"c3"; wait for clk_period;
|
ip_tx.data.data_out <= x"c3"; wait for clk_period;
|
ip_tx.data.data_out <= x"c4"; wait for clk_period;
|
ip_tx.data.data_out <= x"c4"; wait for clk_period;
|
ip_tx.data.data_out <= x"c5"; wait for clk_period;
|
ip_tx.data.data_out <= x"c5"; wait for clk_period;
|
|
|
ip_tx.data.data_out <= x"c6";
|
ip_tx.data.data_out <= x"c6";
|
ip_tx.data.data_out_last <= '1';
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ip_tx.data.data_out_last <= '1';
|
wait for clk_period;
|
wait for clk_period;
|
|
|
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
|
assert mac_data_out_last = '1' report "T1: mac_datda_out_last not set on last byte";
|
|
|
|
|
ip_tx.data.data_out_valid <= '0';
|
ip_tx.data.data_out_valid <= '0';
|
ip_tx.data.data_out_last <= '0';
|
ip_tx.data.data_out_last <= '0';
|
wait for clk_period*2;
|
wait for clk_period*2;
|
|
|
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
|
assert ip_tx_result = IPTX_RESULT_SENT report "T1: result should be IPTX_RESULT_SENT";
|
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
|
assert mac_tx_req = '0' report "T1: mac_tx_req held on too long after TX";
|
|
|
mac_tx_granted <= '0';
|
mac_tx_granted <= '0';
|
wait for clk_period*2;
|
wait for clk_period*2;
|
|
|
report "--- end of tests ---";
|
report "--- end of tests ---";
|
|
|
wait;
|
wait;
|
end process;
|
end process;
|
|
|
END;
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END;
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