----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Company:
|
-- Company:
|
-- Engineer: Peter Fall
|
-- Engineer: Peter Fall
|
--
|
--
|
-- Create Date: 5 June 2011
|
-- Create Date: 5 June 2011
|
-- Design Name:
|
-- Design Name:
|
-- Module Name: UDP_RX - Behavioral
|
-- Module Name: UDP_RX - Behavioral
|
-- Project Name:
|
-- Project Name:
|
-- Target Devices:
|
-- Target Devices:
|
-- Tool versions:
|
-- Tool versions:
|
-- Description:
|
-- Description:
|
-- handle simple UDP RX
|
-- handle simple UDP RX
|
-- doesnt check the checsum
|
-- doesnt check the checsum
|
-- Dependencies:
|
-- Dependencies:
|
--
|
--
|
-- Revision:
|
-- Revision:
|
-- Revision 0.01 - File Created
|
-- Revision 0.01 - File Created
|
-- Revision 0.02 - Improved error handling
|
-- Revision 0.02 - Improved error handling
|
-- Additional Comments:
|
-- Additional Comments:
|
--
|
--
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
library IEEE;
|
library IEEE;
|
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.all;
|
use IEEE.NUMERIC_STD.ALL;
|
use IEEE.NUMERIC_STD.all;
|
use work.axi.all;
|
use work.axi.all;
|
use work.ipv4_types.all;
|
use work.ipv4_types.all;
|
|
|
entity UDP_RX is
|
entity UDP_RX is
|
Port (
|
port (
|
-- UDP Layer signals
|
-- UDP Layer signals
|
udp_rx_start : out std_logic; -- indicates receipt of udp header
|
udp_rx_start : out std_logic; -- indicates receipt of udp header
|
udp_rxo : out udp_rx_type;
|
udp_rxo : out udp_rx_type;
|
-- system signals
|
-- system signals
|
clk : in STD_LOGIC;
|
clk : in std_logic;
|
reset : in STD_LOGIC;
|
reset : in std_logic;
|
-- IP layer RX signals
|
-- IP layer RX signals
|
ip_rx_start : in std_logic; -- indicates receipt of ip header
|
ip_rx_start : in std_logic; -- indicates receipt of ip header
|
ip_rx : in ipv4_rx_type
|
ip_rx : in ipv4_rx_type
|
);
|
);
|
end UDP_RX;
|
end UDP_RX;
|
|
|
architecture Behavioral of UDP_RX is
|
architecture Behavioral of UDP_RX is
|
|
|
type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
|
type rx_state_type is (IDLE, UDP_HDR, USER_DATA, WAIT_END, ERR);
|
|
|
type rx_event_type is (NO_EVENT,DATA);
|
type rx_event_type is (NO_EVENT, DATA);
|
type count_mode_type is (RST, INCR, HOLD);
|
type count_mode_type is (RST, INCR, HOLD);
|
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
|
type settable_count_mode_type is (RST, INCR, SET_VAL, HOLD);
|
type set_clr_type is (SET, CLR, HOLD);
|
type set_clr_type is (SET, CLR, HOLD);
|
|
|
|
|
-- state variables
|
-- state variables
|
signal rx_state : rx_state_type;
|
signal rx_state : rx_state_type;
|
signal rx_count : unsigned (15 downto 0);
|
signal rx_count : unsigned (15 downto 0);
|
signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
|
signal src_port : std_logic_vector (15 downto 0); -- src port captured from input
|
signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
|
signal dst_port : std_logic_vector (15 downto 0); -- dst port captured from input
|
signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
|
signal data_len : std_logic_vector (15 downto 0); -- user data length captured from input
|
signal udp_rx_start_reg : std_logic; -- indicates start of user data
|
signal udp_rx_start_reg : std_logic; -- indicates start of user data
|
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
|
signal hdr_valid_reg : std_logic; -- indicates that hdr data is valid
|
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
|
signal src_ip_addr : std_logic_vector (31 downto 0); -- captured from IP hdr
|
|
|
-- rx control signals
|
-- rx control signals
|
signal next_rx_state : rx_state_type;
|
signal next_rx_state : rx_state_type;
|
signal set_rx_state : std_logic;
|
signal set_rx_state : std_logic;
|
signal rx_event : rx_event_type;
|
signal rx_event : rx_event_type;
|
signal rx_count_mode : settable_count_mode_type;
|
signal rx_count_mode : settable_count_mode_type;
|
signal rx_count_val : unsigned (15 downto 0);
|
signal rx_count_val : unsigned (15 downto 0);
|
signal set_sph : std_logic;
|
signal set_sph : std_logic;
|
signal set_spl : std_logic;
|
signal set_spl : std_logic;
|
signal set_dph : std_logic;
|
signal set_dph : std_logic;
|
signal set_dpl : std_logic;
|
signal set_dpl : std_logic;
|
signal set_len_H : std_logic;
|
signal set_len_H : std_logic;
|
signal set_len_L : std_logic;
|
signal set_len_L : std_logic;
|
signal set_udp_rx_start : set_clr_type;
|
signal set_udp_rx_start : set_clr_type;
|
signal set_hdr_valid : set_clr_type;
|
signal set_hdr_valid : set_clr_type;
|
signal dataval : std_logic_vector (7 downto 0);
|
signal dataval : std_logic_vector (7 downto 0);
|
signal set_pkt_cnt : count_mode_type;
|
signal set_pkt_cnt : count_mode_type;
|
signal set_src_ip : std_logic;
|
signal set_src_ip : std_logic;
|
signal set_data_last : std_logic;
|
signal set_data_last : std_logic;
|
|
|
-- IP datagram header format
|
-- IP datagram header format
|
--
|
--
|
-- 0 4 8 16 19 24 31
|
-- 0 4 8 16 19 24 31
|
-- --------------------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------------------
|
-- | source port number | dest port number |
|
-- | source port number | dest port number |
|
-- | | |
|
-- | | |
|
-- --------------------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------------------
|
-- | length (bytes) | checksum |
|
-- | length (bytes) | checksum |
|
-- | (header and data combined) | |
|
-- | (header and data combined) | |
|
-- --------------------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------------------
|
-- | Data |
|
-- | Data |
|
-- | |
|
-- | |
|
-- --------------------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------------------
|
-- | .... |
|
-- | .... |
|
-- | |
|
-- | |
|
-- --------------------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------------------
|
|
|
|
|
begin
|
begin
|
|
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
-- combinatorial process to implement FSM and determine control signals
|
-- combinatorial process to implement FSM and determine control signals
|
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
|
|
rx_combinatorial : process (
|
rx_combinatorial : process (
|
-- input signals
|
-- input signals
|
ip_rx, ip_rx_start,
|
ip_rx, ip_rx_start,
|
-- state variables
|
-- state variables
|
rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
|
rx_state, rx_count, src_port, dst_port, data_len, udp_rx_start_reg, hdr_valid_reg, src_ip_addr,
|
-- control signals
|
-- control signals
|
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
|
next_rx_state, set_rx_state, rx_event, rx_count_mode, rx_count_val,
|
set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
|
set_sph, set_spl, set_dph, set_dpl, set_len_H, set_len_L, set_data_last,
|
set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
|
set_udp_rx_start, set_hdr_valid, dataval, set_pkt_cnt, set_src_ip
|
)
|
)
|
begin
|
begin
|
-- set output followers
|
-- set output followers
|
udp_rx_start <= udp_rx_start_reg;
|
udp_rx_start <= udp_rx_start_reg;
|
udp_rxo.hdr.is_valid <= hdr_valid_reg;
|
udp_rxo.hdr.is_valid <= hdr_valid_reg;
|
udp_rxo.hdr.data_length <= data_len;
|
udp_rxo.hdr.data_length <= data_len;
|
udp_rxo.hdr.src_port <= src_port;
|
udp_rxo.hdr.src_port <= src_port;
|
udp_rxo.hdr.dst_port <= dst_port;
|
udp_rxo.hdr.dst_port <= dst_port;
|
udp_rxo.hdr.src_ip_addr <= src_ip_addr;
|
udp_rxo.hdr.src_ip_addr <= src_ip_addr;
|
|
|
-- transfer data upstream if in user data phase
|
-- transfer data upstream if in user data phase
|
if rx_state = USER_DATA then
|
if rx_state = USER_DATA then
|
udp_rxo.data.data_in <= ip_rx.data.data_in;
|
udp_rxo.data.data_in <= ip_rx.data.data_in;
|
udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
|
udp_rxo.data.data_in_valid <= ip_rx.data.data_in_valid;
|
udp_rxo.data.data_in_last <= set_data_last;
|
udp_rxo.data.data_in_last <= set_data_last;
|
else
|
else
|
udp_rxo.data.data_in <= (others => '0');
|
udp_rxo.data.data_in <= (others => '0');
|
udp_rxo.data.data_in_valid <= '0';
|
udp_rxo.data.data_in_valid <= '0';
|
udp_rxo.data.data_in_last <= '0';
|
udp_rxo.data.data_in_last <= '0';
|
end if;
|
end if;
|
|
|
-- set signal defaults
|
-- set signal defaults
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_rx_state <= '0';
|
set_rx_state <= '0';
|
rx_event <= NO_EVENT;
|
rx_event <= NO_EVENT;
|
rx_count_mode <= HOLD;
|
rx_count_mode <= HOLD;
|
set_sph <= '0';
|
set_sph <= '0';
|
set_spl <= '0';
|
set_spl <= '0';
|
set_dph <= '0';
|
set_dph <= '0';
|
set_dpl <= '0';
|
set_dpl <= '0';
|
set_len_H <= '0';
|
set_len_H <= '0';
|
set_len_L <= '0';
|
set_len_L <= '0';
|
set_udp_rx_start <= HOLD;
|
set_udp_rx_start <= HOLD;
|
set_hdr_valid <= HOLD;
|
set_hdr_valid <= HOLD;
|
dataval <= (others => '0');
|
dataval <= (others => '0');
|
set_src_ip <= '0';
|
set_src_ip <= '0';
|
rx_count_val <= (others => '0');
|
rx_count_val <= (others => '0');
|
set_data_last <= '0';
|
set_data_last <= '0';
|
|
|
-- determine event (if any)
|
-- determine event (if any)
|
if ip_rx.data.data_in_valid = '1' then
|
if ip_rx.data.data_in_valid = '1' then
|
rx_event <= DATA;
|
rx_event <= DATA;
|
dataval <= ip_rx.data.data_in;
|
dataval <= ip_rx.data.data_in;
|
end if;
|
end if;
|
|
|
-- RX FSM
|
-- RX FSM
|
case rx_state is
|
case rx_state is
|
when IDLE =>
|
when IDLE =>
|
rx_count_mode <= RST;
|
rx_count_mode <= RST;
|
case rx_event is
|
case rx_event is
|
when NO_EVENT => -- (nothing to do)
|
when NO_EVENT => -- (nothing to do)
|
when DATA =>
|
when DATA =>
|
if ip_rx.hdr.protocol = x"11" then
|
if ip_rx.hdr.protocol = x"11" then
|
-- UDP protocol
|
-- UDP protocol
|
rx_count_mode <= INCR;
|
rx_count_mode <= INCR;
|
set_hdr_valid <= CLR;
|
set_hdr_valid <= CLR;
|
set_src_ip <= '1';
|
set_src_ip <= '1';
|
set_sph <= '1';
|
set_sph <= '1';
|
next_rx_state <= UDP_HDR;
|
next_rx_state <= UDP_HDR;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
else
|
else
|
-- non-UDP protocol - ignore this pkt
|
-- non-UDP protocol - ignore this pkt
|
set_hdr_valid <= CLR;
|
set_hdr_valid <= CLR;
|
next_rx_state <= WAIT_END;
|
next_rx_state <= WAIT_END;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
when UDP_HDR =>
|
when UDP_HDR =>
|
case rx_event is
|
case rx_event is
|
when NO_EVENT => -- (nothing to do)
|
when NO_EVENT => -- (nothing to do)
|
when DATA =>
|
when DATA =>
|
if rx_count = x"0007" then
|
if rx_count = x"0007" then
|
rx_count_mode <= SET_VAL;
|
rx_count_mode <= SET_VAL;
|
rx_count_val <= x"0001";
|
rx_count_val <= x"0001";
|
next_rx_state <= USER_DATA;
|
next_rx_state <= USER_DATA;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
else
|
else
|
rx_count_mode <= INCR;
|
rx_count_mode <= INCR;
|
end if;
|
end if;
|
-- handle early frame termination
|
-- handle early frame termination
|
if ip_rx.data.data_in_last = '1' then
|
if ip_rx.data.data_in_last = '1' then
|
next_rx_state <= ERR;
|
next_rx_state <= ERR;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
else
|
else
|
case rx_count is
|
case rx_count is
|
when x"0000" => set_sph <= '1';
|
when x"0000" => set_sph <= '1';
|
when x"0001" => set_spl <= '1';
|
when x"0001" => set_spl <= '1';
|
when x"0002" => set_dph <= '1';
|
when x"0002" => set_dph <= '1';
|
when x"0003" => set_dpl <= '1';
|
when x"0003" => set_dpl <= '1';
|
|
|
when x"0004" => set_len_H <= '1';
|
when x"0004" => set_len_H <= '1';
|
when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
|
when x"0005" => set_len_L <= '1'; set_hdr_valid <= SET; -- header values are now valid, although the pkt may not be for us
|
|
|
when x"0006" => -- ignore checksum values
|
when x"0006" => -- ignore checksum values
|
when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
|
when x"0007" => set_udp_rx_start <= SET; -- indicate frame received
|
|
|
|
|
when others => -- ignore other bytes in udp header
|
when others => -- ignore other bytes in udp header
|
end case;
|
end case;
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
when USER_DATA =>
|
when USER_DATA =>
|
case rx_event is
|
case rx_event is
|
when NO_EVENT => -- (nothing to do)
|
when NO_EVENT => -- (nothing to do)
|
when DATA =>
|
when DATA =>
|
-- note: data gets transfered upstream as part of "output followers" processing
|
-- note: data gets transfered upstream as part of "output followers" processing
|
if rx_count = unsigned(data_len) then
|
if rx_count = unsigned(data_len) then
|
set_udp_rx_start <= CLR;
|
set_udp_rx_start <= CLR;
|
rx_count_mode <= RST;
|
rx_count_mode <= RST;
|
set_data_last <= '1';
|
set_data_last <= '1';
|
if ip_rx.data.data_in_last = '1' then
|
if ip_rx.data.data_in_last = '1' then
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_udp_rx_start <= CLR;
|
set_udp_rx_start <= CLR;
|
else
|
else
|
next_rx_state <= WAIT_END;
|
next_rx_state <= WAIT_END;
|
end if;
|
end if;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
else
|
else
|
rx_count_mode <= INCR;
|
rx_count_mode <= INCR;
|
-- check for early frame termination
|
-- check for early frame termination
|
-- TODO need to mark frame as errored
|
-- TODO need to mark frame as errored
|
if ip_rx.data.data_in_last = '1' then
|
if ip_rx.data.data_in_last = '1' then
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
set_data_last <= '1';
|
set_data_last <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
when ERR =>
|
when ERR =>
|
if ip_rx.data.data_in_last = '0' then
|
if ip_rx.data.data_in_last = '0' then
|
next_rx_state <= WAIT_END;
|
next_rx_state <= WAIT_END;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
else
|
else
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
end if;
|
end if;
|
|
|
|
|
when WAIT_END =>
|
when WAIT_END =>
|
case rx_event is
|
case rx_event is
|
when NO_EVENT => -- (nothing to do)
|
when NO_EVENT => -- (nothing to do)
|
when DATA =>
|
when DATA =>
|
if ip_rx.data.data_in_last = '1' then
|
if ip_rx.data.data_in_last = '1' then
|
next_rx_state <= IDLE;
|
next_rx_state <= IDLE;
|
set_rx_state <= '1';
|
set_rx_state <= '1';
|
end if;
|
end if;
|
end case;
|
end case;
|
|
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- sequential process to action control signals and change states and outputs
|
-- sequential process to action control signals and change states and outputs
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
rx_sequential : process (clk,reset)
|
rx_sequential : process (clk, reset)
|
begin
|
begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
if reset = '1' then
|
if reset = '1' then
|
-- reset state variables
|
-- reset state variables
|
rx_state <= IDLE;
|
rx_state <= IDLE;
|
rx_count <= x"0000";
|
rx_count <= x"0000";
|
src_port <= (others => '0');
|
src_port <= (others => '0');
|
dst_port <= (others => '0');
|
dst_port <= (others => '0');
|
data_len <= (others => '0');
|
data_len <= (others => '0');
|
udp_rx_start_reg <= '0';
|
udp_rx_start_reg <= '0';
|
hdr_valid_reg <= '0';
|
hdr_valid_reg <= '0';
|
src_ip_addr <= (others => '0');
|
src_ip_addr <= (others => '0');
|
else
|
else
|
-- Next rx_state processing
|
-- Next rx_state processing
|
if set_rx_state = '1' then
|
if set_rx_state = '1' then
|
rx_state <= next_rx_state;
|
rx_state <= next_rx_state;
|
else
|
else
|
rx_state <= rx_state;
|
rx_state <= rx_state;
|
end if;
|
end if;
|
|
|
-- rx_count processing
|
-- rx_count processing
|
case rx_count_mode is
|
case rx_count_mode is
|
when RST => rx_count <= x"0000";
|
when RST => rx_count <= x"0000";
|
when INCR => rx_count <= rx_count + 1;
|
when INCR => rx_count <= rx_count + 1;
|
when SET_VAL => rx_count <= rx_count_val;
|
when SET_VAL => rx_count <= rx_count_val;
|
when HOLD => rx_count <= rx_count;
|
when HOLD => rx_count <= rx_count;
|
end case;
|
end case;
|
|
|
-- port number capture
|
-- port number capture
|
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
|
if (set_sph = '1') then src_port(15 downto 8) <= dataval; end if;
|
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
|
if (set_spl = '1') then src_port(7 downto 0) <= dataval; end if;
|
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
|
if (set_dph = '1') then dst_port(15 downto 8) <= dataval; end if;
|
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
|
if (set_dpl = '1') then dst_port(7 downto 0) <= dataval; end if;
|
|
|
if (set_len_H = '1') then
|
if (set_len_H = '1') then
|
data_len (15 downto 8) <= dataval;
|
data_len (15 downto 8) <= dataval;
|
data_len (7 downto 0) <= x"00";
|
data_len (7 downto 0) <= x"00";
|
elsif (set_len_L = '1') then
|
elsif (set_len_L = '1') then
|
-- compute data length, taking into account that we need to subtract the header length
|
-- compute data length, taking into account that we need to subtract the header length
|
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
|
data_len <= std_logic_vector(unsigned(data_len(15 downto 8) & dataval) - 8);
|
else
|
else
|
data_len <= data_len;
|
data_len <= data_len;
|
end if;
|
end if;
|
|
|
case set_udp_rx_start is
|
case set_udp_rx_start is
|
when SET => udp_rx_start_reg <= '1';
|
when SET => udp_rx_start_reg <= '1';
|
when CLR => udp_rx_start_reg <= '0';
|
when CLR => udp_rx_start_reg <= '0';
|
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
|
when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
|
end case;
|
end case;
|
|
|
-- capture src IP address
|
-- capture src IP address
|
if set_src_ip = '1' then
|
if set_src_ip = '1' then
|
src_ip_addr <= ip_rx.hdr.src_ip_addr;
|
src_ip_addr <= ip_rx.hdr.src_ip_addr;
|
else
|
else
|
src_ip_addr <= src_ip_addr;
|
src_ip_addr <= src_ip_addr;
|
end if;
|
end if;
|
|
|
case set_hdr_valid is
|
case set_hdr_valid is
|
when SET => hdr_valid_reg <= '1';
|
when SET => hdr_valid_reg <= '1';
|
when CLR => hdr_valid_reg <= '0';
|
when CLR => hdr_valid_reg <= '0';
|
when HOLD => hdr_valid_reg <= hdr_valid_reg;
|
when HOLD => hdr_valid_reg <= hdr_valid_reg;
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
|
|
