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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.arp_types.all;
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use work.arp_types.all;
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entity arp_STORE_br is
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entity arp_STORE_br is
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generic (
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generic (
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
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);
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);
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Port (
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port (
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-- read signals
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-- read signals
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read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
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read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
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read_result : out arp_store_result_t; -- the result
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read_result : out arp_store_result_t; -- the result
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-- write signals
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-- write signals
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write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
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write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
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-- control and status signals
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-- control and status signals
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clear_store : in std_logic; -- erase all entries
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clear_store : in std_logic; -- erase all entries
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entry_count : out unsigned(7 downto 0); -- how many entries currently in store
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entry_count : out unsigned(7 downto 0); -- how many entries currently in store
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-- system signals
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-- system signals
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clk : in std_logic;
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clk : in std_logic;
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reset : in STD_LOGIC
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reset : in std_logic
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);
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);
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end arp_STORE_br;
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end arp_STORE_br;
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architecture Behavioral of arp_STORE_br is
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architecture Behavioral of arp_STORE_br is
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-- busses
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-- busses
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signal next_st_state : st_state_t;
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signal next_st_state : st_state_t;
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signal arp_entry_val : arp_entry_t;
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signal arp_entry_val : arp_entry_t;
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signal mode_val : mode_t;
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signal mode_val : mode_t;
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signal write_addr : addr_t; -- actual write address to use
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signal write_addr : addr_t; -- actual write address to use
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signal read_result_int : arp_store_result_t;
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-- control signals
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-- control signals
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signal set_st_state : std_logic;
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signal set_st_state : std_logic;
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signal set_next_write_addr : count_mode_t;
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signal set_next_write_addr : count_mode_t;
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signal set_num_entries : count_mode_t;
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signal set_num_entries : count_mode_t;
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read_req, write_req, clear_store, reset,
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read_req, write_req, clear_store, reset,
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-- state variables
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-- state variables
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ip_ram, mac_ram, st_state, next_write_addr, num_entries,
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ip_ram, mac_ram, st_state, next_write_addr, num_entries,
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next_read_addr, entry_found, mode, req_entry,
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next_read_addr, entry_found, mode, req_entry,
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-- busses
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-- busses
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next_st_state, arp_entry_val, mode_val, write_addr,
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next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
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-- control signals
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-- control signals
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set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
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set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
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write_ram, set_mode
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write_ram, set_mode
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)
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)
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begin
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begin
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-- set output followers
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-- set output followers
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read_result.status <= IDLE;
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read_result_int.status <= IDLE;
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read_result.entry <= entry_found;
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read_result_int.entry <= entry_found;
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entry_count <= to_unsigned(num_entries,8);
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entry_count <= to_unsigned(num_entries,8);
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-- set bus defaults
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-- set bus defaults
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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mode_val <= MREAD;
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mode_val <= MREAD;
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set_st_state <= '1';
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set_st_state <= '1';
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end if;
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end if;
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when PAUSE =>
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when PAUSE =>
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-- wait until read addr is latched and we get first data out of the ram
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-- wait until read addr is latched and we get first data out of the ram
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read_result.status <= read_status(BUSY,mode);
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read_result_int.status <= read_status(BUSY, mode);
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set_next_read_addr <= INCR;
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set_next_read_addr <= INCR;
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next_st_state <= SEARCH;
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next_st_state <= SEARCH;
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set_st_state <= '1';
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set_st_state <= '1';
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when SEARCH =>
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when SEARCH =>
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read_result.status <= read_status(SEARCHING,mode);
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read_result_int.status <= read_status(SEARCHING, mode);
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-- check if have a match at this entry
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-- check if have a match at this entry
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if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
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if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
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-- found it
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-- found it
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set_entry_found <= '1';
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set_entry_found <= '1';
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next_st_state <= FOUND;
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next_st_state <= FOUND;
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set_st_state <= '1';
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set_st_state <= '1';
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elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
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elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
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-- reached end of entry table
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-- reached end of entry table
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read_result.status <= read_status(NOT_FOUND,mode);
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read_result_int.status <= read_status(NOT_FOUND, mode);
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next_st_state <= NOT_FOUND;
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next_st_state <= NOT_FOUND;
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set_st_state <= '1';
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set_st_state <= '1';
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else
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else
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-- no match at this entry , go to next
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-- no match at this entry , go to next
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set_next_read_addr <= INCR;
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set_next_read_addr <= INCR;
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end if;
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end if;
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when FOUND =>
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when FOUND =>
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read_result.status <= read_status(FOUND,mode);
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read_result_int.status <= read_status(FOUND, mode);
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if mode = MWRITE then
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if mode = MWRITE then
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write_addr <= next_read_addr - 1;
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write_addr <= next_read_addr - 1;
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write_ram <= '1';
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write_ram <= '1';
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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set_st_state <= '1';
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set_st_state <= '1';
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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set_st_state <= '1';
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set_st_state <= '1';
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end if;
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end if;
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when NOT_FOUND =>
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when NOT_FOUND =>
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read_result.status <= read_status(NOT_FOUND,mode);
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read_result_int.status <= read_status(NOT_FOUND, mode);
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if mode = MWRITE then
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if mode = MWRITE then
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-- need to write into the next free slot
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-- need to write into the next free slot
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write_addr <= next_write_addr;
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write_addr <= next_write_addr;
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write_ram <= '1';
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write_ram <= '1';
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set_next_write_addr <= INCR;
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set_next_write_addr <= INCR;
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else
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else
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arp_entry_val.ip <= (others => '0');
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arp_entry_val.ip <= (others => '0');
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arp_entry_val.mac <= (others => '0');
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arp_entry_val.mac <= (others => '0');
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end if;
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end if;
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read_result <= read_result_int;
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if reset = '1' or clear_store = '1' then
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if reset = '1' or clear_store = '1' then
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-- reset state variables
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-- reset state variables
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st_state <= IDLE;
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st_state <= IDLE;
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next_write_addr <= 0;
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next_write_addr <= 0;
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num_entries <= 0;
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num_entries <= 0;
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