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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [arp_STORE_br.vhd] - Diff between revs 10 and 18

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Rev 10 Rev 18
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-- Revision 0.01 - File Created
-- Revision 0.01 - File Created
-- Additional Comments: 
-- Additional Comments: 
--
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
use work.arp_types.all;
use work.arp_types.all;
 
 
entity arp_STORE_br is
entity arp_STORE_br is
        generic (
        generic (
                        MAX_ARP_ENTRIES : integer := 255                                                        -- max entries in the store
                        MAX_ARP_ENTRIES : integer := 255                                                        -- max entries in the store
                        );
                        );
        Port (
  port (
                        -- read signals
                        -- read signals
                        read_req                                : in arp_store_rdrequest_t;             -- requesting a lookup or store
                        read_req                                : in arp_store_rdrequest_t;             -- requesting a lookup or store
                        read_result                     : out arp_store_result_t;                       -- the result
                        read_result                     : out arp_store_result_t;                       -- the result
                        -- write signals
                        -- write signals
                        write_req                       : in arp_store_wrrequest_t;             -- requesting a lookup or store
                        write_req                       : in arp_store_wrrequest_t;             -- requesting a lookup or store
                        -- control and status signals
                        -- control and status signals
                        clear_store                     : in std_logic;                                         -- erase all entries
                        clear_store                     : in std_logic;                                         -- erase all entries
                        entry_count                     : out unsigned(7 downto 0);              -- how many entries currently in store
                        entry_count                     : out unsigned(7 downto 0);              -- how many entries currently in store
                        -- system signals
                        -- system signals
                        clk                                     : in std_logic;
                        clk                                     : in std_logic;
                        reset                           : in  STD_LOGIC
    reset       : in  std_logic
                        );
                        );
end arp_STORE_br;
end arp_STORE_br;
 
 
architecture Behavioral of arp_STORE_br is
architecture Behavioral of arp_STORE_br is
 
 
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        -- busses
        -- busses
        signal next_st_state                    : st_state_t;
        signal next_st_state                    : st_state_t;
        signal arp_entry_val                    : arp_entry_t;
        signal arp_entry_val                    : arp_entry_t;
        signal mode_val                         : mode_t;
        signal mode_val                         : mode_t;
        signal write_addr                               : addr_t;                                                                               -- actual write address to use
        signal write_addr                               : addr_t;                                                                               -- actual write address to use
 
  signal read_result_int        : arp_store_result_t;
 
 
        -- control signals
        -- control signals
        signal set_st_state             : std_logic;
        signal set_st_state             : std_logic;
        signal set_next_write_addr      : count_mode_t;
        signal set_next_write_addr      : count_mode_t;
        signal set_num_entries          : count_mode_t;
        signal set_num_entries          : count_mode_t;
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                read_req, write_req, clear_store, reset,
                read_req, write_req, clear_store, reset,
                -- state variables
                -- state variables
                ip_ram, mac_ram, st_state, next_write_addr, num_entries,
                ip_ram, mac_ram, st_state, next_write_addr, num_entries,
                next_read_addr, entry_found, mode, req_entry,
                next_read_addr, entry_found, mode, req_entry,
                -- busses
                -- busses
                next_st_state, arp_entry_val, mode_val, write_addr,
    next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
                -- control signals
                -- control signals
                set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
                set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
                write_ram, set_mode
                write_ram, set_mode
                )
                )
        begin
        begin
                -- set output followers
                -- set output followers
                read_result.status <= IDLE;
    read_result_int.status <= IDLE;
                read_result.entry <= entry_found;
    read_result_int.entry  <= entry_found;
                entry_count <= to_unsigned(num_entries,8);
                entry_count <= to_unsigned(num_entries,8);
 
 
                -- set bus defaults
                -- set bus defaults
                next_st_state <= IDLE;
                next_st_state <= IDLE;
                mode_val <= MREAD;
                mode_val <= MREAD;
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                                        set_st_state <= '1';
                                        set_st_state <= '1';
                                end if;
                                end if;
 
 
                        when PAUSE =>
                        when PAUSE =>
                                -- wait until read addr is latched and we get first data out of the ram
                                -- wait until read addr is latched and we get first data out of the ram
                                read_result.status <= read_status(BUSY,mode);
        read_result_int.status <= read_status(BUSY, mode);
                                set_next_read_addr <= INCR;
                                set_next_read_addr <= INCR;
                                next_st_state <= SEARCH;
                                next_st_state <= SEARCH;
                                set_st_state <= '1';
                                set_st_state <= '1';
 
 
                        when SEARCH =>
                        when SEARCH =>
                                read_result.status <= read_status(SEARCHING,mode);
        read_result_int.status                                    <= read_status(SEARCHING, mode);
                                -- check if have a match at this entry
                                -- check if have a match at this entry
                                if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
                                if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
                                        -- found it
                                        -- found it
                                        set_entry_found <= '1';
                                        set_entry_found <= '1';
                                        next_st_state <= FOUND;
                                        next_st_state <= FOUND;
                                        set_st_state <= '1';
                                        set_st_state <= '1';
                                elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
                                elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
                                        -- reached end of entry table
                                        -- reached end of entry table
                                        read_result.status <= read_status(NOT_FOUND,mode);
          read_result_int.status <= read_status(NOT_FOUND, mode);
                                        next_st_state <= NOT_FOUND;
                                        next_st_state <= NOT_FOUND;
                                        set_st_state <= '1';
                                        set_st_state <= '1';
                                else
                                else
                                        -- no match at this entry , go to next
                                        -- no match at this entry , go to next
                                        set_next_read_addr <= INCR;
                                        set_next_read_addr <= INCR;
                                end if;
                                end if;
 
 
                        when FOUND =>
                        when FOUND =>
                                read_result.status <= read_status(FOUND,mode);
        read_result_int.status <= read_status(FOUND, mode);
                                if mode = MWRITE then
                                if mode = MWRITE then
                                        write_addr <= next_read_addr - 1;
                                        write_addr <= next_read_addr - 1;
                                        write_ram <= '1';
                                        write_ram <= '1';
                                        next_st_state <= IDLE;
                                        next_st_state <= IDLE;
                                        set_st_state <= '1';
                                        set_st_state <= '1';
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                                        next_st_state <= IDLE;
                                        next_st_state <= IDLE;
                                        set_st_state <= '1';
                                        set_st_state <= '1';
                                end if;
                                end if;
 
 
                        when NOT_FOUND =>
                        when NOT_FOUND =>
                                read_result.status <= read_status(NOT_FOUND,mode);
        read_result_int.status <= read_status(NOT_FOUND, mode);
                                if mode = MWRITE then
                                if mode = MWRITE then
                                        -- need to write into the next free slot
                                        -- need to write into the next free slot
                                        write_addr <= next_write_addr;
                                        write_addr <= next_write_addr;
                                        write_ram <= '1';
                                        write_ram <= '1';
                                        set_next_write_addr <= INCR;
                                        set_next_write_addr <= INCR;
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                        else
                        else
                                arp_entry_val.ip <= (others => '0');
                                arp_entry_val.ip <= (others => '0');
                                arp_entry_val.mac <= (others => '0');
                                arp_entry_val.mac <= (others => '0');
                        end if;
                        end if;
 
 
 
      read_result <= read_result_int;
 
 
                        if reset = '1' or clear_store = '1' then
                        if reset = '1' or clear_store = '1' then
                                -- reset state variables
                                -- reset state variables
                                st_state <= IDLE;
                                st_state <= IDLE;
                                next_write_addr <= 0;
                                next_write_addr <= 0;
                                num_entries <= 0;
                                num_entries <= 0;

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