----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer: Peter Fall
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-- Engineer: Peter Fall
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--
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--
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-- Create Date: 12:00:04 05/31/2011
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-- Create Date: 12:00:04 05/31/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: arp_STORE_br - Behavioral
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-- Module Name: arp_STORE_br - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description:
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-- Description:
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-- ARP storage table using block ram with lookup based on IP address
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-- ARP storage table using block ram with lookup based on IP address
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-- implements upto 255 entries with sequential search
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-- implements upto 255 entries with sequential search
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-- uses round robin overwrite when full (LRU would be better, but ...)
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-- uses round robin overwrite when full (LRU would be better, but ...)
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--
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--
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-- store may take a number of cycles and the request is latched
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-- store may take a number of cycles and the request is latched
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-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
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-- lookup may take a number of cycles. Assumes that request signals remain valid during lookup
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.NUMERIC_STD.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use work.arp_types.all;
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use work.arp_types.all;
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entity arp_STORE_br is
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entity arp_STORE_br is
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generic (
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generic (
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
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MAX_ARP_ENTRIES : integer := 255 -- max entries in the store
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);
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);
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Port (
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port (
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-- read signals
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-- read signals
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read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
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read_req : in arp_store_rdrequest_t; -- requesting a lookup or store
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read_result : out arp_store_result_t; -- the result
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read_result : out arp_store_result_t; -- the result
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-- write signals
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-- write signals
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write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
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write_req : in arp_store_wrrequest_t; -- requesting a lookup or store
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-- control and status signals
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-- control and status signals
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clear_store : in std_logic; -- erase all entries
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clear_store : in std_logic; -- erase all entries
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entry_count : out unsigned(7 downto 0); -- how many entries currently in store
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entry_count : out unsigned(7 downto 0); -- how many entries currently in store
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-- system signals
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-- system signals
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clk : in std_logic;
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clk : in std_logic;
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reset : in STD_LOGIC
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reset : in std_logic
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);
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);
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end arp_STORE_br;
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end arp_STORE_br;
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architecture Behavioral of arp_STORE_br is
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architecture Behavioral of arp_STORE_br is
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type st_state_t is (IDLE,PAUSE,SEARCH,FOUND,NOT_FOUND);
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type st_state_t is (IDLE, PAUSE, SEARCH, FOUND, NOT_FOUND);
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type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
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type ip_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(31 downto 0);
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type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
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type mac_ram_t is array (0 to MAX_ARP_ENTRIES-1) of std_logic_vector(47 downto 0);
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subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
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subtype addr_t is integer range 0 to MAX_ARP_ENTRIES;
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type count_mode_t is (RST,INCR,HOLD);
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type count_mode_t is (RST, INCR, HOLD);
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type mode_t is (MREAD,MWRITE);
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type mode_t is (MREAD, MWRITE);
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-- state variables
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-- state variables
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signal ip_ram : ip_ram_t; -- will be implemented as block ram
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signal ip_ram : ip_ram_t; -- will be implemented as block ram
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signal mac_ram : mac_ram_t; -- will be implemented as block ram
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signal mac_ram : mac_ram_t; -- will be implemented as block ram
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signal st_state : st_state_t;
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signal st_state : st_state_t;
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signal next_write_addr : addr_t; -- where to make the next write
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signal next_write_addr : addr_t; -- where to make the next write
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signal num_entries : addr_t; -- number of entries in the store
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signal num_entries : addr_t; -- number of entries in the store
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signal next_read_addr : addr_t; -- next addr to read from
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signal next_read_addr : addr_t; -- next addr to read from
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signal entry_found : arp_entry_t; -- entry found in search
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signal entry_found : arp_entry_t; -- entry found in search
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signal mode : mode_t; -- are we writing or reading?
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signal mode : mode_t; -- are we writing or reading?
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signal req_entry : arp_entry_t; -- entry latched from req
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signal req_entry : arp_entry_t; -- entry latched from req
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-- busses
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-- busses
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signal next_st_state : st_state_t;
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signal next_st_state : st_state_t;
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signal arp_entry_val : arp_entry_t;
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signal arp_entry_val : arp_entry_t;
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signal mode_val : mode_t;
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signal mode_val : mode_t;
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signal write_addr : addr_t; -- actual write address to use
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signal write_addr : addr_t; -- actual write address to use
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signal read_result_int : arp_store_result_t;
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-- control signals
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-- control signals
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signal set_st_state : std_logic;
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signal set_st_state : std_logic;
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signal set_next_write_addr : count_mode_t;
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signal set_next_write_addr : count_mode_t;
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signal set_num_entries : count_mode_t;
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signal set_num_entries : count_mode_t;
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signal set_next_read_addr : count_mode_t;
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signal set_next_read_addr : count_mode_t;
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signal write_ram : std_logic;
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signal write_ram : std_logic;
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signal set_entry_found : std_logic;
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signal set_entry_found : std_logic;
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signal set_mode : std_logic;
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signal set_mode : std_logic;
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function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
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function read_status(status : arp_store_rslt_t; signal mode : mode_t) return arp_store_rslt_t is
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variable ret : arp_store_rslt_t;
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variable ret : arp_store_rslt_t;
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begin
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begin
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case status is
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case status is
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when IDLE =>
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when IDLE =>
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ret := status;
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ret := status;
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when others =>
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when others =>
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if mode = MWRITE then
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if mode = MWRITE then
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ret := BUSY;
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ret := BUSY;
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else
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else
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ret := status;
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ret := status;
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end if;
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end if;
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end case;
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end case;
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return ret;
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return ret;
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end read_status;
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end read_status;
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begin
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begin
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combinatorial : process (
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combinatorial : process (
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-- input signals
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-- input signals
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read_req, write_req, clear_store, reset,
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read_req, write_req, clear_store, reset,
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-- state variables
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-- state variables
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ip_ram, mac_ram, st_state, next_write_addr, num_entries,
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ip_ram, mac_ram, st_state, next_write_addr, num_entries,
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next_read_addr, entry_found, mode, req_entry,
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next_read_addr, entry_found, mode, req_entry,
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-- busses
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-- busses
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next_st_state, arp_entry_val, mode_val, write_addr,
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next_st_state, arp_entry_val, mode_val, write_addr, read_result_int,
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-- control signals
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-- control signals
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set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
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set_st_state, set_next_write_addr, set_num_entries, set_next_read_addr, set_entry_found,
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write_ram, set_mode
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write_ram, set_mode
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)
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)
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begin
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begin
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-- set output followers
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-- set output followers
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read_result.status <= IDLE;
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read_result_int.status <= IDLE;
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read_result.entry <= entry_found;
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read_result_int.entry <= entry_found;
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entry_count <= to_unsigned(num_entries,8);
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entry_count <= to_unsigned(num_entries,8);
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-- set bus defaults
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-- set bus defaults
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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mode_val <= MREAD;
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mode_val <= MREAD;
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write_addr <= next_write_addr;
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write_addr <= next_write_addr;
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-- set signal defaults
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-- set signal defaults
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set_st_state <= '0';
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set_st_state <= '0';
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set_next_write_addr <= HOLD;
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set_next_write_addr <= HOLD;
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set_num_entries <= HOLD;
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set_num_entries <= HOLD;
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set_next_read_addr <= HOLD;
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set_next_read_addr <= HOLD;
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write_ram <= '0';
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write_ram <= '0';
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set_entry_found <= '0';
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set_entry_found <= '0';
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set_mode <= '0';
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set_mode <= '0';
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-- STORE FSM
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-- STORE FSM
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case st_state is
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case st_state is
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when IDLE =>
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when IDLE =>
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if write_req.req = '1' then
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if write_req.req = '1' then
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-- need to search to see if this IP already there
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-- need to search to see if this IP already there
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set_next_read_addr <= RST; -- start lookup from beginning
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set_next_read_addr <= RST; -- start lookup from beginning
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mode_val <= MWRITE;
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mode_val <= MWRITE;
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set_mode <= '1';
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set_mode <= '1';
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next_st_state <= PAUSE;
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next_st_state <= PAUSE;
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set_st_state <= '1';
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set_st_state <= '1';
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elsif read_req.req = '1' then
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elsif read_req.req = '1' then
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set_next_read_addr <= RST; -- start lookup from beginning
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set_next_read_addr <= RST; -- start lookup from beginning
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mode_val <= MREAD;
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mode_val <= MREAD;
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set_mode <= '1';
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set_mode <= '1';
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next_st_state <= PAUSE;
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next_st_state <= PAUSE;
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set_st_state <= '1';
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set_st_state <= '1';
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end if;
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end if;
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when PAUSE =>
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when PAUSE =>
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-- wait until read addr is latched and we get first data out of the ram
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-- wait until read addr is latched and we get first data out of the ram
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read_result.status <= read_status(BUSY,mode);
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read_result_int.status <= read_status(BUSY, mode);
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set_next_read_addr <= INCR;
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set_next_read_addr <= INCR;
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next_st_state <= SEARCH;
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next_st_state <= SEARCH;
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set_st_state <= '1';
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set_st_state <= '1';
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when SEARCH =>
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when SEARCH =>
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read_result.status <= read_status(SEARCHING,mode);
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read_result_int.status <= read_status(SEARCHING, mode);
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-- check if have a match at this entry
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-- check if have a match at this entry
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if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
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if req_entry.ip = arp_entry_val.ip and next_read_addr <= num_entries then
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-- found it
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-- found it
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set_entry_found <= '1';
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set_entry_found <= '1';
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next_st_state <= FOUND;
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next_st_state <= FOUND;
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set_st_state <= '1';
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set_st_state <= '1';
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elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
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elsif next_read_addr > num_entries or next_read_addr >= MAX_ARP_ENTRIES then
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-- reached end of entry table
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-- reached end of entry table
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read_result.status <= read_status(NOT_FOUND,mode);
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read_result_int.status <= read_status(NOT_FOUND, mode);
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next_st_state <= NOT_FOUND;
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next_st_state <= NOT_FOUND;
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set_st_state <= '1';
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set_st_state <= '1';
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else
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else
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-- no match at this entry , go to next
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-- no match at this entry , go to next
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set_next_read_addr <= INCR;
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set_next_read_addr <= INCR;
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end if;
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end if;
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when FOUND =>
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when FOUND =>
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read_result.status <= read_status(FOUND,mode);
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read_result_int.status <= read_status(FOUND, mode);
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if mode = MWRITE then
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if mode = MWRITE then
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write_addr <= next_read_addr - 1;
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write_addr <= next_read_addr - 1;
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write_ram <= '1';
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write_ram <= '1';
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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set_st_state <= '1';
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set_st_state <= '1';
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elsif read_req.req = '0' then -- wait in this state until request de-asserted
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elsif read_req.req = '0' then -- wait in this state until request de-asserted
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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set_st_state <= '1';
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set_st_state <= '1';
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end if;
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end if;
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when NOT_FOUND =>
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when NOT_FOUND =>
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read_result.status <= read_status(NOT_FOUND,mode);
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read_result_int.status <= read_status(NOT_FOUND, mode);
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if mode = MWRITE then
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if mode = MWRITE then
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-- need to write into the next free slot
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-- need to write into the next free slot
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write_addr <= next_write_addr;
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write_addr <= next_write_addr;
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write_ram <= '1';
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write_ram <= '1';
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set_next_write_addr <= INCR;
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set_next_write_addr <= INCR;
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if num_entries < MAX_ARP_ENTRIES then
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if num_entries < MAX_ARP_ENTRIES then
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-- if not full, count another entry (if full, it just wraps)
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-- if not full, count another entry (if full, it just wraps)
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set_num_entries <= INCR;
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set_num_entries <= INCR;
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end if;
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end if;
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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set_st_state <= '1';
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set_st_state <= '1';
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elsif read_req.req = '0' then -- wait in this state until request de-asserted
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elsif read_req.req = '0' then -- wait in this state until request de-asserted
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next_st_state <= IDLE;
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next_st_state <= IDLE;
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set_st_state <= '1';
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set_st_state <= '1';
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end if;
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end if;
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end case;
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end case;
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end process;
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end process;
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sequential : process (clk)
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sequential : process (clk)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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-- ram processing
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-- ram processing
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if write_ram = '1' then
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if write_ram = '1' then
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ip_ram(write_addr) <= req_entry.ip;
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ip_ram(write_addr) <= req_entry.ip;
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mac_ram(write_addr) <= req_entry.mac;
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mac_ram(write_addr) <= req_entry.mac;
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end if;
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end if;
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if next_read_addr < MAX_ARP_ENTRIES then
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if next_read_addr < MAX_ARP_ENTRIES then
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arp_entry_val.ip <= ip_ram(next_read_addr);
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arp_entry_val.ip <= ip_ram(next_read_addr);
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arp_entry_val.mac <= mac_ram(next_read_addr);
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arp_entry_val.mac <= mac_ram(next_read_addr);
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else
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else
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arp_entry_val.ip <= (others => '0');
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arp_entry_val.ip <= (others => '0');
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arp_entry_val.mac <= (others => '0');
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arp_entry_val.mac <= (others => '0');
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end if;
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end if;
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read_result <= read_result_int;
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|
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if reset = '1' or clear_store = '1' then
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if reset = '1' or clear_store = '1' then
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-- reset state variables
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-- reset state variables
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st_state <= IDLE;
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st_state <= IDLE;
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next_write_addr <= 0;
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next_write_addr <= 0;
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num_entries <= 0;
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num_entries <= 0;
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next_read_addr <= 0;
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next_read_addr <= 0;
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entry_found.ip <= (others => '0');
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entry_found.ip <= (others => '0');
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entry_found.mac <= (others => '0');
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entry_found.mac <= (others => '0');
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req_entry.ip <= (others => '0');
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req_entry.ip <= (others => '0');
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req_entry.mac <= (others => '0');
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req_entry.mac <= (others => '0');
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mode <= MREAD;
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mode <= MREAD;
|
|
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else
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else
|
-- Next req_state processing
|
-- Next req_state processing
|
if set_st_state = '1' then
|
if set_st_state = '1' then
|
st_state <= next_st_state;
|
st_state <= next_st_state;
|
else
|
else
|
st_state <= st_state;
|
st_state <= st_state;
|
end if;
|
end if;
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|
|
-- mode setting and write request latching
|
-- mode setting and write request latching
|
if set_mode = '1' then
|
if set_mode = '1' then
|
mode <= mode_val;
|
mode <= mode_val;
|
if mode_val = MWRITE then
|
if mode_val = MWRITE then
|
req_entry <= write_req.entry;
|
req_entry <= write_req.entry;
|
else
|
else
|
req_entry.ip <= read_req.ip;
|
req_entry.ip <= read_req.ip;
|
req_entry.mac <= (others => '0');
|
req_entry.mac <= (others => '0');
|
end if;
|
end if;
|
else
|
else
|
mode <= mode;
|
mode <= mode;
|
req_entry <= req_entry;
|
req_entry <= req_entry;
|
end if;
|
end if;
|
|
|
-- latch entry found
|
-- latch entry found
|
if set_entry_found = '1' then
|
if set_entry_found = '1' then
|
entry_found <= arp_entry_val;
|
entry_found <= arp_entry_val;
|
else
|
else
|
entry_found <= entry_found;
|
entry_found <= entry_found;
|
end if;
|
end if;
|
|
|
-- next_write_addr counts and wraps
|
-- next_write_addr counts and wraps
|
case set_next_write_addr is
|
case set_next_write_addr is
|
when HOLD => next_write_addr <= next_write_addr;
|
when HOLD => next_write_addr <= next_write_addr;
|
when RST => next_write_addr <= 0;
|
when RST => next_write_addr <= 0;
|
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
|
when INCR => if next_write_addr < MAX_ARP_ENTRIES-1 then next_write_addr <= next_write_addr + 1; else next_write_addr <= 0; end if;
|
end case;
|
end case;
|
|
|
-- num_entries counts and holds at max
|
-- num_entries counts and holds at max
|
case set_num_entries is
|
case set_num_entries is
|
when HOLD => num_entries <= num_entries;
|
when HOLD => num_entries <= num_entries;
|
when RST => num_entries <= 0;
|
when RST => num_entries <= 0;
|
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
|
when INCR => if next_write_addr < MAX_ARP_ENTRIES then num_entries <= num_entries + 1; else num_entries <= num_entries; end if;
|
end case;
|
end case;
|
|
|
-- next_read_addr counts and wraps
|
-- next_read_addr counts and wraps
|
case set_next_read_addr is
|
case set_next_read_addr is
|
when HOLD => next_read_addr <= next_read_addr;
|
when HOLD => next_read_addr <= next_read_addr;
|
when RST => next_read_addr <= 0;
|
when RST => next_read_addr <= 0;
|
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
|
when INCR => if next_read_addr < MAX_ARP_ENTRIES then next_read_addr <= next_read_addr + 1; else next_read_addr <= 0; end if;
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
end Behavioral;
|
end Behavioral;
|
|
|
