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----------------------------------------------------------------------------------
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-- Company:
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-- Company:
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-- Engineer:
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-- Engineer:
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--
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--
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-- Create Date: 08:03:30 06/04/2011
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-- Create Date: 08:03:30 06/04/2011
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-- Design Name:
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-- Design Name:
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-- Module Name: tx_arbitrator - Behavioral
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-- Module Name: tx_arbitrator - Behavioral
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-- Project Name:
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-- Project Name:
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-- Target Devices:
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-- Target Devices:
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-- Tool versions:
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-- Tool versions:
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-- Description: arbitrate between two sources that want to transmit onto a bus
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-- Description: arbitrate between two sources that want to transmit onto a bus
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-- handles arbitration and multiplexing
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-- handles arbitration and multiplexing
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--
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--
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-- Dependencies:
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-- Dependencies:
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--
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.01 - File Created
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-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
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-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
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-- Revision 0.03 - Added first
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-- Additional Comments:
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-- Additional Comments:
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity tx_arbitrator is
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entity tx_arbitrator is
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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req_1 : in std_logic;
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req_1 : in std_logic;
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grant_1 : out std_logic;
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grant_1 : out std_logic;
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data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
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data_1 : in std_logic_vector(7 downto 0); -- data byte to tx
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valid_1 : in std_logic; -- tdata is valid
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valid_1 : in std_logic; -- tdata is valid
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first_1 : in std_logic; -- indicates first byte of frame
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last_1 : in std_logic; -- indicates last byte of frame
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last_1 : in std_logic; -- indicates last byte of frame
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req_2 : in std_logic;
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req_2 : in std_logic;
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grant_2 : out std_logic;
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grant_2 : out std_logic;
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data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
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data_2 : in std_logic_vector(7 downto 0); -- data byte to tx
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valid_2 : in std_logic; -- tdata is valid
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valid_2 : in std_logic; -- tdata is valid
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first_2 : in std_logic; -- indicates first byte of frame
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last_2 : in std_logic; -- indicates last byte of frame
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last_2 : in std_logic; -- indicates last byte of frame
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data : out std_logic_vector(7 downto 0); -- data byte to tx
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data : out std_logic_vector(7 downto 0); -- data byte to tx
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valid : out std_logic; -- tdata is valid
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valid : out std_logic; -- tdata is valid
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first : out std_logic; -- indicates first byte of frame
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last : out std_logic -- indicates last byte of frame
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last : out std_logic -- indicates last byte of frame
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);
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);
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end tx_arbitrator;
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end tx_arbitrator;
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architecture Behavioral of tx_arbitrator is
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architecture Behavioral of tx_arbitrator is
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type grant_type is (M1,M2);
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type grant_type is (M1,M2);
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signal grant : grant_type;
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signal grant : grant_type;
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begin
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begin
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combinatorial : process (
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combinatorial : process (
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grant,
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grant,
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data_1, valid_1, last_1,
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data_1, valid_1, first_1, last_1,
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data_2, valid_2, last_2
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data_2, valid_2, first_2, last_2
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)
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)
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begin
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begin
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-- grant outputs
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-- grant outputs
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case grant is
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case grant is
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when M1 =>
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when M1 =>
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grant_1 <= '1';
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grant_1 <= '1';
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grant_2 <= '0';
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grant_2 <= '0';
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when M2 =>
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when M2 =>
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grant_1 <= '0';
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grant_1 <= '0';
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grant_2 <= '1';
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grant_2 <= '1';
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end case;
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end case;
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-- multiplexer
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-- multiplexer
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if grant = M1 then
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if grant = M1 then
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data <= data_1;
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data <= data_1;
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valid <= valid_1;
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valid <= valid_1;
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first <= first_1;
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last <= last_1;
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last <= last_1;
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else
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else
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data <= data_2;
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data <= data_2;
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valid <= valid_2;
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valid <= valid_2;
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first <= first_2;
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last <= last_2;
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last <= last_2;
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end if;
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end if;
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end process;
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end process;
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sequential : process (clk, reset, req_1, req_2, grant)
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sequential : process (clk, reset, req_1, req_2, grant)
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if reset = '1' then
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if reset = '1' then
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grant <= M1;
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grant <= M1;
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else
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else
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case grant is
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case grant is
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when M1 =>
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when M1 =>
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if req_1 = '1' then
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if req_1 = '1' then
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grant <= M1;
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grant <= M1;
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elsif req_2 = '1' then
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elsif req_2 = '1' then
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grant <= M2;
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grant <= M2;
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end if;
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end if;
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when M2 =>
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when M2 =>
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if req_2 = '1' then
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if req_2 = '1' then
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grant <= M2;
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grant <= M2;
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else
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else
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grant <= M1;
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grant <= M1;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end Behavioral;
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end Behavioral;
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