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Line 1... |
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--======================================================================================--
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--======================================================================================--
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-- Verilog to VHDL conversion by Martin Neumann martin@neumnns-mail.de --
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-- Verilog to VHDL conversion by Martin Neumann martin@neumnns-mail.de --
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-- --
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-- --
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-- /////////////////////////////////////////////////////////////////// --
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-- /////////////////////////////////////////////////////////////////// --
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-- // // --
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-- // // --
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| Line 43... |
Line 44... |
-- --
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-- --
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-- Change history --
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-- Change history --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- | Vers. | Date | Autor | Comment | --
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-- | Vers. | Date | Autor | Comment | --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- +-------+-----------+-------+------------------------------------------------------+ --
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-- | 1.0 |04 Feb 2011| MN | Initial version | --
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-- | 2.0 | 3 Jul 2016| MN | Changed eop logic due to USB spec violation | --
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-- | 1.1 |23 Apr 2011| MN | Added missing 'rst' in process sensitivity lists | --
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-- | 1.1 |23 Apr 2011| MN | Added missing 'rst' in process sensitivity lists | --
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-- | | | | Added ELSE constructs in next_state process to | --
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-- | | | | Added ELSE constructs in next_state process to | --
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-- | | | | prevent an undesired latch implementation. | --
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-- | | | | prevent an undesired latch implementation. | --
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-- | 1.0 |04 Feb 2011| MN | Initial version | --
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--======================================================================================--
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--======================================================================================--
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|
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library ieee;
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LIBRARY ieee;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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USE ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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|
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entity usb_tx_phy is
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ENTITY usb_tx_phy is
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port (
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PORT (
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clk : in std_logic;
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clk : IN STD_LOGIC;
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rst : in std_logic;
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rst : IN STD_LOGIC;
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fs_ce : in std_logic;
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fs_ce : IN STD_LOGIC;
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phy_mode : in std_logic;
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phy_mode : IN STD_LOGIC; -- HIGH level for differential IO mode (else single-ended)
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-- Transciever Interface
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-- Transciever Interface
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txdp, txdn, txoe : out std_logic;
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txdp, txdn, txoe : OUT STD_LOGIC;
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-- UTMI Interface
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-- UTMI Interface
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DataOut_i : in std_logic_vector(7 downto 0);
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DataOut_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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TxValid_i : in std_logic;
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TxValid_i : IN STD_LOGIC;
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TxReady_o : out std_logic
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TxReady_o : OUT STD_LOGIC
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);
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);
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end usb_tx_phy;
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END usb_tx_phy;
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|
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architecture RTL of usb_tx_phy is
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ARCHITECTURE RTL of usb_tx_phy is
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|
|
signal hold_reg : std_logic_vector(7 downto 0);
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SIGNAL hold_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal ld_data : std_logic;
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SIGNAL ld_data : STD_LOGIC;
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signal ld_data_d : std_logic;
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SIGNAL ld_data_d : STD_LOGIC;
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signal ld_eop_d : std_logic;
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SIGNAL ld_sop_d : STD_LOGIC;
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signal ld_sop_d : std_logic;
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SIGNAL bit_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);
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signal bit_cnt : std_logic_vector(2 downto 0);
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SIGNAL sft_done_e : STD_LOGIC;
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signal sft_done_e : std_logic;
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SIGNAL any_eop_state : STD_LOGIC;
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signal append_eop : std_logic;
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SIGNAL append_eop : STD_LOGIC;
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signal append_eop_sync1 : std_logic;
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SIGNAL data_xmit : STD_LOGIC;
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signal append_eop_sync2 : std_logic;
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SIGNAL hold_reg_d : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal append_eop_sync3 : std_logic;
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SIGNAL one_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);
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signal append_eop_sync4 : std_logic;
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SIGNAL sd_bs_o : STD_LOGIC;
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signal data_done : std_logic;
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SIGNAL sd_nrzi_o : STD_LOGIC;
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signal eop_done : std_logic;
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SIGNAL sd_raw_o : STD_LOGIC;
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signal hold_reg_d : std_logic_vector(7 downto 0);
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SIGNAL sft_done : STD_LOGIC;
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signal one_cnt : std_logic_vector(2 downto 0);
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SIGNAL sft_done_r : STD_LOGIC;
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signal sd_bs_o : std_logic;
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SIGNAL state : STD_LOGIC_VECTOR(3 DOWNTO 0);
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signal sd_nrzi_o : std_logic;
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SIGNAL stuff : STD_LOGIC;
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signal sd_raw_o : std_logic;
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SIGNAL tx_ip : STD_LOGIC;
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signal sft_done : std_logic;
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SIGNAL tx_ip_sync : STD_LOGIC;
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signal sft_done_r : std_logic;
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SIGNAL txoe_r1, txoe_r2 : STD_LOGIC;
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signal state, next_state : std_logic_vector(2 downto 0);
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|
signal stuff : std_logic;
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CONSTANT IDLE_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
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signal tx_ip : std_logic;
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CONSTANT SOP_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
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signal tx_ip_sync : std_logic;
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CONSTANT DATA_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
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signal txoe_r1, txoe_r2 : std_logic;
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CONSTANT WAIT_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
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CONSTANT EOP0_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
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constant IDLE_STATE : std_logic_vector := "000";
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CONSTANT EOP1_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
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constant SOP_STATE : std_logic_vector := "001";
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CONSTANT EOP2_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";
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constant DATA_STATE : std_logic_vector := "010";
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CONSTANT EOP3_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
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constant EOP1_STATE : std_logic_vector := "011";
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CONSTANT EOP4_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
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constant EOP2_STATE : std_logic_vector := "100";
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CONSTANT EOP5_STATE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1101";
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constant WAIT_STATE : std_logic_vector := "101";
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|
|
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begin
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BEGIN
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|
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--======================================================================================--
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--======================================================================================--
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-- Misc Logic --
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-- Misc Logic --
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--======================================================================================--
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--======================================================================================--
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|
|
p_TxReady_o: process (clk, rst)
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p_TxReady_o: PROCESS (clk, rst)
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begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
TxReady_o <= '0';
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TxReady_o <= '0';
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elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
TxReady_o <= ld_data_d and TxValid_i;
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TxReady_o <= ld_data_d AND TxValid_i;
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end if;
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END IF;
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end process;
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END PROCESS;
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|
|
p_ld_data: process (clk)
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p_ld_data: PROCESS (clk)
|
begin
|
BEGIN
|
if rising_edge(clk) then
|
IF rising_edge(clk) THEN
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ld_data <= ld_data_d;
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ld_data <= ld_data_d;
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end if;
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END IF;
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end process;
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END PROCESS;
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--======================================================================================--
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--======================================================================================--
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-- Transmit in progress indicator --
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-- Transmit in progress indicator --
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--======================================================================================--
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--======================================================================================--
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p_tx_ip: process (clk, rst)
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p_tx_ip: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
tx_ip <= '0';
|
tx_ip <= '0';
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elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if ld_sop_d ='1' then
|
IF ld_sop_d ='1' THEN
|
tx_ip <= '1';
|
tx_ip <= '1';
|
elsif eop_done ='1' then
|
ELSIF append_eop ='1' THEN
|
tx_ip <= '0';
|
tx_ip <= '0';
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
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|
|
p_tx_ip_sync: process (clk, rst)
|
p_tx_ip_sync: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
tx_ip_sync <= '0';
|
tx_ip_sync <= '0';
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elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if fs_ce ='1' then
|
IF fs_ce ='1' THEN
|
tx_ip_sync <= tx_ip;
|
tx_ip_sync <= tx_ip;
|
end if;
|
END IF;
|
end if;
|
END IF;
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end process;
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END PROCESS;
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|
|
-- data_done helps us to catch cases where TxValid drops due to
|
-- data_xmit helps us to catch cases where TxValid drops due to
|
-- packet end and then gets re-asserted as a new packet starts.
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-- packet END and then gets re-asserted as a new packet starts.
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-- We might not see this because we are still transmitting.
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-- We might not see this because we are still transmitting.
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-- data_done should solve those cases ...
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-- data_xmit should solve those cases ...
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p_data_done: process (clk, rst)
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p_data_xmit: PROCESS (clk, rst)
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begin
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BEGIN
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if rst ='0' then
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IF rst ='0' THEN
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data_done <= '0';
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data_xmit <= '0';
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elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
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if TxValid_i ='1' and tx_ip ='0' then
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IF TxValid_i ='1' AND tx_ip ='0' THEN
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data_done <= '1';
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data_xmit <= '1';
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elsif TxValid_i = '0' then
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ELSIF TxValid_i = '0' THEN
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data_done <= '0';
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data_xmit <= '0';
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end if;
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END IF;
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end if;
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END IF;
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end process;
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END PROCESS;
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--======================================================================================--
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--======================================================================================--
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-- Shift Register --
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-- Shift Register --
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--======================================================================================--
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--======================================================================================--
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p_bit_cnt: process (clk, rst)
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p_bit_cnt: PROCESS (clk, rst)
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begin
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BEGIN
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if rst ='0' then
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IF rst ='0' THEN
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bit_cnt <= "000";
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bit_cnt <= "000";
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elsif rising_edge(clk) then
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ELSIF rising_edge(clk) THEN
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if tx_ip_sync ='0' then
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IF tx_ip_sync ='0' THEN
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bit_cnt <= "000";
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bit_cnt <= "000";
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elsif fs_ce ='1' and stuff ='0' then
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ELSIF fs_ce ='1' AND stuff ='0' THEN
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bit_cnt <= bit_cnt + 1;
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bit_cnt <= bit_cnt + 1;
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end if;
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END IF;
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end if;
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END IF;
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end process;
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END PROCESS;
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|
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p_sd_raw_o: process (clk)
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p_sd_raw_o: PROCESS (clk)
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begin
|
BEGIN
|
if rising_edge(clk) then
|
IF rising_edge(clk) THEN
|
if tx_ip_sync ='0' then
|
IF tx_ip_sync ='0' THEN
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sd_raw_o <= '0';
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sd_raw_o <= '0';
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else
|
ELSE
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sd_raw_o <= hold_reg_d(CONV_INTEGER(UNSIGNED(bit_cnt)));
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sd_raw_o <= hold_reg_d(CONV_INTEGER(UNSIGNED(bit_cnt)));
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end if;
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END IF;
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end if;
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END IF;
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end process;
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END PROCESS;
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p_sft_done: process (clk)
|
p_sft_done: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rising_edge(clk) then
|
IF rst ='0' THEN
|
if bit_cnt = "111" then
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|
sft_done <= not stuff;
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|
else
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|
sft_done <= '0';
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sft_done <= '0';
|
end if;
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sft_done_r <= '0';
|
end if;
|
ELSIF rising_edge(clk) THEN
|
end process;
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IF bit_cnt = "111" THEN
|
|
sft_done <= NOT stuff;
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p_sft_done_r: process (clk)
|
ELSE
|
begin
|
sft_done <= '0';
|
if rising_edge(clk) then
|
END IF;
|
sft_done_r <= sft_done;
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sft_done_r <= sft_done;
|
end if;
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END IF;
|
end process;
|
END PROCESS;
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|
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sft_done_e <= sft_done and not sft_done_r;
|
sft_done_e <= sft_done AND NOT sft_done_r;
|
|
|
-- Out Data Hold Register
|
-- Out Data Hold Register
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p_hold_reg: process (clk, rst)
|
p_hold_reg: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
hold_reg <= X"00";
|
hold_reg <= X"00";
|
hold_reg_d <= X"00";
|
hold_reg_d <= X"00";
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if ld_sop_d ='1' then
|
IF ld_sop_d ='1' THEN
|
hold_reg <= X"80";
|
hold_reg <= X"80";
|
elsif ld_data ='1' then
|
ELSIF ld_data ='1' THEN
|
hold_reg <= DataOut_i;
|
hold_reg <= DataOut_i;
|
end if;
|
END IF;
|
hold_reg_d <= hold_reg;
|
hold_reg_d <= hold_reg;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
--======================================================================================--
|
--======================================================================================--
|
-- Bit Stuffer --
|
-- Bit Stuffer --
|
--======================================================================================--
|
--======================================================================================--
|
|
|
p_one_cnt: process (clk, rst)
|
p_one_cnt: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
one_cnt <= "000";
|
one_cnt <= "000";
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if tx_ip_sync ='0' then
|
IF tx_ip_sync ='0' THEN
|
one_cnt <= "000";
|
one_cnt <= "000";
|
elsif fs_ce ='1' then
|
ELSIF fs_ce ='1' THEN
|
if sd_raw_o ='0' or stuff = '1' then
|
IF sd_raw_o ='0' OR stuff = '1' THEN
|
one_cnt <= "000";
|
one_cnt <= "000";
|
else
|
ELSE
|
one_cnt <= one_cnt + 1;
|
one_cnt <= one_cnt + 1;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
stuff <= '1' when one_cnt = "110" else '0';
|
stuff <= '1' WHEN one_cnt = "110" ELSE '0';
|
|
|
p_sd_bs_o: process (clk, rst)
|
p_sd_bs_o: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
sd_bs_o <= '0';
|
sd_bs_o <= '0';
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if fs_ce ='1' then
|
IF fs_ce ='1' THEN
|
if tx_ip_sync ='0' then
|
IF tx_ip_sync ='0' THEN
|
sd_bs_o <= '0';
|
sd_bs_o <= '0';
|
else
|
ELSE
|
if stuff ='1' then
|
IF stuff ='1' THEN
|
sd_bs_o <= '0';
|
sd_bs_o <= '0';
|
else
|
ELSE
|
sd_bs_o <= sd_raw_o;
|
sd_bs_o <= sd_raw_o;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
--======================================================================================--
|
--======================================================================================--
|
-- NRZI Encoder --
|
-- NRZI Encoder --
|
--======================================================================================--
|
--======================================================================================--
|
|
|
p_sd_nrzi_o: process (clk, rst)
|
p_sd_nrzi_o: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
sd_nrzi_o <= '1';
|
sd_nrzi_o <= '1';
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if tx_ip_sync ='0' or txoe_r1 ='0' then
|
IF tx_ip_sync ='0' OR txoe_r1 ='0' THEN
|
sd_nrzi_o <= '1';
|
sd_nrzi_o <= '1';
|
elsif fs_ce ='1' then
|
ELSIF fs_ce ='1' THEN
|
if sd_bs_o ='1' then
|
IF sd_bs_o ='1' THEN
|
sd_nrzi_o <= sd_nrzi_o;
|
sd_nrzi_o <= sd_nrzi_o;
|
else
|
ELSE
|
sd_nrzi_o <= not sd_nrzi_o;
|
sd_nrzi_o <= NOT sd_nrzi_o;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
--======================================================================================--
|
|
-- EOP append logic --
|
|
--======================================================================================--
|
|
|
|
p_append_eop: process (clk, rst)
|
|
begin
|
|
if rst ='0' then
|
|
append_eop <= '0';
|
|
elsif rising_edge(clk) then
|
|
if ld_eop_d ='1' then
|
|
append_eop <= '1';
|
|
elsif append_eop_sync2 ='1' then
|
|
append_eop <= '0';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
p_append_eop_sync: process (clk, rst)
|
|
begin
|
|
if rst ='0' then
|
|
append_eop_sync1 <= '0';
|
|
append_eop_sync2 <= '0';
|
|
append_eop_sync3 <= '0';
|
|
append_eop_sync4 <= '0';
|
|
elsif rising_edge(clk) then
|
|
if fs_ce ='1' then
|
|
append_eop_sync1 <= append_eop;
|
|
append_eop_sync2 <= append_eop_sync1;
|
|
append_eop_sync3 <= append_eop_sync2 or -- Make sure always 2 bit wide
|
|
(append_eop_sync3 and not append_eop_sync4);
|
|
append_eop_sync4 <= append_eop_sync3;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
eop_done <= append_eop_sync3;
|
|
|
|
--======================================================================================--
|
--======================================================================================--
|
-- Output Enable Logic --
|
-- Output Enable Logic --
|
--======================================================================================--
|
--======================================================================================--
|
|
|
p_txoe: process (clk, rst)
|
p_txoe: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
txoe_r1 <= '0';
|
txoe_r1 <= '0';
|
txoe_r2 <= '0';
|
txoe_r2 <= '0';
|
txoe <= '1';
|
txoe <= '1';
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if fs_ce ='1' then
|
IF fs_ce ='1' THEN
|
txoe_r1 <= tx_ip_sync;
|
txoe_r1 <= tx_ip_sync;
|
txoe_r2 <= txoe_r1;
|
txoe_r2 <= txoe_r1;
|
txoe <= not (txoe_r1 or txoe_r2);
|
txoe <= NOT (txoe_r1 OR txoe_r2);
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
--======================================================================================--
|
--======================================================================================--
|
-- Output Registers --
|
-- Output Registers --
|
--======================================================================================--
|
--======================================================================================--
|
|
|
p_txdpn: process (clk, rst)
|
p_txdpn: PROCESS (clk, rst)
|
begin
|
BEGIN
|
if rst ='0' then
|
IF rst ='0' THEN
|
txdp <= '1';
|
txdp <= '1';
|
txdn <= '0';
|
txdn <= '0';
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
if fs_ce ='1' then
|
IF fs_ce ='1' THEN
|
if phy_mode ='1' then
|
IF phy_mode ='1' THEN
|
txdp <= not append_eop_sync3 and sd_nrzi_o;
|
txdp <= NOT append_eop AND sd_nrzi_o;
|
txdn <= not append_eop_sync3 and not sd_nrzi_o;
|
txdn <= NOT append_eop AND NOT sd_nrzi_o;
|
else
|
ELSE
|
txdp <= sd_nrzi_o;
|
txdp <= sd_nrzi_o;
|
txdn <= append_eop_sync3;
|
txdn <= append_eop;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
--======================================================================================--
|
--======================================================================================--
|
-- Tx Statemashine --
|
-- Tx Statemashine --
|
--======================================================================================--
|
--======================================================================================--
|
|
|
p_state: process (clk, rst)
|
any_eop_state <= state(3);
|
begin
|
|
if rst ='0' then
|
p_state: PROCESS (clk, rst)
|
|
BEGIN
|
|
IF rst ='0' THEN
|
state <= IDLE_STATE;
|
state <= IDLE_STATE;
|
elsif rising_edge(clk) then
|
ELSIF rising_edge(clk) THEN
|
state <= next_state;
|
IF any_eop_state = '0' THEN
|
end if;
|
CASE (state) IS
|
end process;
|
WHEN IDLE_STATE => IF TxValid_i ='1' THEN
|
|
state <= SOP_STATE;
|
p_next_state: process (rst, state, TxValid_i, data_done, sft_done_e, eop_done, fs_ce)
|
END IF;
|
begin
|
WHEN SOP_STATE => IF sft_done_e ='1' THEN
|
if rst='0' then
|
state <= DATA_STATE;
|
next_state <= IDLE_STATE;
|
END IF;
|
else
|
WHEN DATA_STATE => IF data_xmit ='0' AND sft_done_e ='1' THEN
|
case (state) is
|
IF one_cnt = "101" AND hold_reg_d(7) = '1' THEN
|
when IDLE_STATE => if TxValid_i ='1' then
|
state <= EOP0_STATE;
|
next_state <= SOP_STATE;
|
|
ELSE
|
ELSE
|
next_state <= IDLE_STATE;
|
state <= EOP1_STATE;
|
end if;
|
END IF;
|
when SOP_STATE => if sft_done_e ='1' then
|
END IF;
|
next_state <= DATA_STATE;
|
WHEN WAIT_STATE => IF fs_ce = '1' THEN
|
ELSE
|
state <= IDLE_STATE;
|
next_state <= SOP_STATE;
|
END IF;
|
end if;
|
WHEN OTHERS => state <= IDLE_STATE;
|
when DATA_STATE => if data_done ='0' and sft_done_e ='1' then
|
END CASE;
|
next_state <= EOP1_STATE;
|
|
ELSE
|
|
next_state <= DATA_STATE;
|
|
end if;
|
|
when EOP1_STATE => if eop_done ='1' then
|
|
next_state <= EOP2_STATE;
|
|
ELSE
|
|
next_state <= EOP1_STATE;
|
|
end if;
|
|
when EOP2_STATE => if eop_done ='0' and fs_ce ='1' then
|
|
next_state <= WAIT_STATE;
|
|
ELSE
|
ELSE
|
next_state <= EOP2_STATE;
|
IF fs_ce ='1' THEN
|
end if;
|
IF state = EOP5_state THEN
|
when WAIT_STATE => if fs_ce = '1' then
|
state <= WAIT_STATE;
|
next_state <= IDLE_STATE;
|
|
ELSE
|
ELSE
|
next_state <= WAIT_STATE;
|
state <= unsigned(state) + 1;
|
end if;
|
END IF;
|
when others => next_state <= IDLE_STATE;
|
END IF;
|
end case;
|
END IF;
|
end if;
|
END IF;
|
end process;
|
END PROCESS;
|
|
|
ld_sop_d <= TxValid_i when state = IDLE_STATE else '0';
|
append_eop <= '1' WHEN state(3 DOWNTO 2) = "11" ELSE '0'; -- EOP4_STATE OR EOP5_STATE
|
ld_data_d <= sft_done_e when state = SOP_STATE or (state = DATA_STATE and data_done ='1') else '0';
|
ld_sop_d <= TxValid_i WHEN state = IDLE_STATE ELSE '0';
|
ld_eop_d <= sft_done_e when state = Data_STATE and data_done ='0' else '0';
|
ld_data_d <= sft_done_e WHEN state = SOP_STATE OR (state = DATA_STATE AND data_xmit ='1') ELSE '0';
|
|
|
end RTL;
|
END RTL;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
