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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity usimplez_cpu is
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entity usimplez_cpu is
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generic(
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generic(
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WIDTH_DATA_BUS: natural:=12;
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WIDTH_WORD: natural:=12;
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WIDTH_OPERATION_CODE: natural:=3;
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WIDTH_OPERATION_CODE: natural:=3;
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WIDTH_ADDRESS: natural:=9;
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WIDTH_ADDRESS: natural:=9;
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--Instructions:
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--Instructions:
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ST: unsigned:="000";
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ST: unsigned:="000";
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LD: unsigned:="001";
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LD: unsigned:="001";
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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data_bus_i: in std_logic_vector((WIDTH_DATA_BUS-1) downto 0);
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data_bus_i: in std_logic_vector((WIDTH_WORD-1) downto 0);
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data_bus_o: out std_logic_vector((WIDTH_DATA_BUS-1) downto 0);
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data_bus_o: out std_logic_vector((WIDTH_WORD-1) downto 0);
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addr_bus_o: out std_logic_vector((WIDTH_ADDRESS-1) downto 0);
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addr_bus_o: out std_logic_vector((WIDTH_ADDRESS-1) downto 0);
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we_o: out std_logic;
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we_o: out std_logic;
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--To Debug:
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--To Debug:
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In0_o: out std_logic;
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In0_o: out std_logic;
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In1_o: out std_logic;
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In1_o: out std_logic;
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architecture fsm of usimplez_cpu is
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architecture fsm of usimplez_cpu is
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type T_estado is (In0,In1,Op0,Op1);
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type T_estado is (In0,In1,Op0,Op1);
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signal estado: T_estado;
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signal estado: T_estado;
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--Bit Cero <- '1' si AC = 0;
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--Registros:
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signal z_bit_s:std_logic;
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--Acumulador (AC)
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--Acumulador (AC)
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signal acumulador: unsigned((WIDTH_DATA_BUS-1) downto 0);
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signal ac_reg_s: unsigned((WIDTH_WORD-1) downto 0);
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--Registro CO
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--Codigo de Operacion (CO)
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signal co_reg_s: unsigned((WIDTH_OPERATION_CODE-1) downto 0);
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signal co_reg_s: unsigned((WIDTH_OPERATION_CODE-1) downto 0);
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--Registro CD
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--Campo de Direccion (CD)
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signal cd_reg_s: unsigned((WIDTH_ADDRESS-1) downto 0);
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signal cd_reg_s: unsigned((WIDTH_ADDRESS-1) downto 0);
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--BD
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--Contador de Programa (CP)
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signal data_bus_s: unsigned((WIDTH_DATA_BUS-1) downto 0);
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--Registro CP
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signal cp_reg_s: unsigned((WIDTH_ADDRESS-1) downto 0);
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signal cp_reg_s: unsigned((WIDTH_ADDRESS-1) downto 0);
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--Bus Dir
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--Buses:
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signal data_bus_s: unsigned((WIDTH_WORD-1) downto 0);
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signal addr_bus_s: unsigned((WIDTH_ADDRESS-1) downto 0);
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signal addr_bus_s: unsigned((WIDTH_ADDRESS-1) downto 0);
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begin
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begin
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process(clk_i,rst_i)
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process(clk_i,rst_i)
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begin
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begin
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if(rising_edge(clk_i)) then
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if(rising_edge(clk_i)) then
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if(rst_i='1') then
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if(rst_i='1') then
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co_reg_s <= (others=>'0');
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co_reg_s <= (others=>'0');
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acumulador <= (others=>'0');
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ac_reg_s <= (others=>'0');
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cd_reg_s <= (others=>'0');
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cd_reg_s <= (others=>'0');
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cp_reg_s <= (others=>'0');
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cp_reg_s <= (others=>'0');
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addr_bus_o <= (others=>'1');
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addr_bus_o <= (others=>'1');
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data_bus_o <= (others=>'0');
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data_bus_o <= (others=>'0');
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we_o<='0';
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we_o<='0';
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estado <= In0;
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estado <= In0;
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--
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--
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else
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else
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case estado is
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case estado is
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when In0 =>
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when In0 =>
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-- (MP[RA])->RI;
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-- (MP[CD])->CO;
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co_reg_s<=unsigned(data_bus_i(11 downto 9));
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co_reg_s<=unsigned(data_bus_i(11 downto 9));
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cd_reg_s<=unsigned(data_bus_i(8 downto 0));
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cd_reg_s<=unsigned(data_bus_i(8 downto 0));
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-- (cp_reg_s)+1->cp_reg_s
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-- (CP)+1->CP
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cp_reg_s<=cp_reg_s+1;
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cp_reg_s<=cp_reg_s+1;
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--
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--
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In0_o<='1';
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In0_o<='1';
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In1_o<='0';
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In1_o<='0';
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Op0_o<='0';
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Op0_o<='0';
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Op1_o<='0';
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Op1_o<='0';
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--
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--
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case (co_reg_s) is
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case (co_reg_s) is
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when CLR =>
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when CLR =>
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-- 0->AC
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-- 0->AC
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acumulador<=(others=>'0');
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ac_reg_s<=(others=>'0');
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-- (cp_reg_s)->RA
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-- (CP)->CD
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addr_bus_o<=std_logic_vector(cp_reg_s);
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addr_bus_o<=std_logic_vector(cp_reg_s);
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estado<=In0;
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estado<=In0;
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when DEC =>
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when DEC =>
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-- (AC)-1 -> AC
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-- (AC)-1 -> AC
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acumulador<=acumulador-1;
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ac_reg_s<=ac_reg_s-1;
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-- (cp_reg_s)->RA
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-- (CP)->CD
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addr_bus_o<=std_logic_vector(cp_reg_s);
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addr_bus_o<=std_logic_vector(cp_reg_s);
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estado<=In0;
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estado<=In0;
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when BR =>
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when BR =>
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-- (cd_reg_s)->cp_reg_s,RA
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-- (CD)->CP,CD
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cp_reg_s<=cd_reg_s;
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cp_reg_s<=cd_reg_s;
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addr_bus_o<=std_logic_vector(cd_reg_s);
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addr_bus_o<=std_logic_vector(cd_reg_s);
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estado<=In0;
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estado<=In0;
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when BZ =>
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when BZ =>
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--Si z_bit_s=1 igual BR
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--Si AC>0 igual BR
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if(acumulador=0) then
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if(ac_reg_s=0) then
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cp_reg_s<=cp_reg_s;
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cp_reg_s<=cp_reg_s;
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addr_bus_o<=std_logic_vector(cd_reg_s);
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addr_bus_o<=std_logic_vector(cd_reg_s);
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else
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else
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--Si no (cp_reg_s)->RA
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--Si no (CP)->CD
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addr_bus_o<=std_logic_vector(cp_reg_s);
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addr_bus_o<=std_logic_vector(cp_reg_s);
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end if;
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end if;
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estado<=In0;
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estado<=In0;
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when HALT =>
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when HALT =>
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-- 0->cp_reg_s
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-- 0->CP
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cp_reg_s<=(others=>'0');
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cp_reg_s<=(others=>'0');
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estado<=In0;
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estado<=In1;
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when LD =>
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when LD =>
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-- (cd_reg_s)->RA
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-- (CD)->CD
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addr_bus_o<=std_logic_vector(cd_reg_s);
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addr_bus_o<=std_logic_vector(cd_reg_s);
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estado<=Op0;
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estado<=Op0;
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when ST =>
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when ST =>
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addr_bus_o<=std_logic_vector(cd_reg_s);
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addr_bus_o<=std_logic_vector(cd_reg_s);
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estado<=Op0;
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estado<=Op0;
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Op0_o<='1';
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Op0_o<='1';
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Op1_o<='0';
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Op1_o<='0';
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--
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--
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case (co_reg_s) is
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case (co_reg_s) is
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when LD =>
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when LD =>
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-- (MP[RA])->AC
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-- (MP[CD])->AC
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acumulador<=unsigned(data_bus_i);
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ac_reg_s<=unsigned(data_bus_i);
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estado<=Op1;
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estado<=Op1;
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when ST =>
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when ST =>
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-- (AC)->MP[RA]
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-- (AC)->MP[CD]
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data_bus_o<=std_logic_vector(acumulador);
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data_bus_o<=std_logic_vector(ac_reg_s);
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we_o<='1';
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we_o<='1';
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estado<=Op1;
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estado<=Op1;
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when ADD =>
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when ADD =>
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acumulador<=acumulador+unsigned(data_bus_i);
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ac_reg_s<=ac_reg_s+unsigned(data_bus_i);
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estado<=Op1;
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estado<=Op1;
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when others =>
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when others =>
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estado<=In0;
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estado<=In0;
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end case;
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end case;
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when OP1 =>
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when OP1 =>
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-- (cp_reg_s)->RA
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-- (CP)->CD
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addr_bus_o<=std_logic_vector(cp_reg_s);
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addr_bus_o<=std_logic_vector(cp_reg_s);
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we_o<='0';
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we_o<='0';
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estado<=In0;
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estado<=In0;
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--
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--
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In0_o<='0';
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In0_o<='0';
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