OpenCores
URL https://opencores.org/ocsvn/v6502/v6502/trunk

Subversion Repositories v6502

[/] [v6502/] [trunk/] [v6502.vhd] - Diff between revs 4 and 6

Show entire file | Details | Blame | View Log

Rev 4 Rev 6
Line 1... Line 1... 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
-- 8 bit microprocessor (65C02) with some enhances VHDL project     -- 
-- 8 bit microprocessor (65C02) with some enhances VHDL project     -- 
-- Full RTL synchronous pipelined architecture                      --
 
-- Full RTL synchronous pipelined architecture                      --
 
-- Project by Valerio Venturi (Italy)                               -- 
-- Project by Valerio Venturi (Italy)                               -- 
-- Date: 14/04/2011                                                 --
 
-- Date: 14/04/2011                                                 --
 
-- Last revision: 05/05/2011                                        --
 
-- Last revision: 19/04/2020                                        --
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
 
 
 
 
-- NOTE:
 
 
 
-- in this version I made some changes on the pr.vhd and mcpla.vhd files because some instructions changed the V flag by mistake
 
 
 
 
 
 
 
 
 
library IEEE;
 
library IEEE;
 
use IEEE.std_logic_1164.all;                             -- defines std_logic types
 
use IEEE.std_logic_1164.all;                             -- defines std_logic types
 
use IEEE.STD_LOGIC_unsigned.all;
 
use IEEE.STD_LOGIC_unsigned.all;
 
use IEEE.STD_LOGIC_arith.all;
 
use IEEE.STD_LOGIC_arith.all;
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.