| Line 51... |
Line 51... |
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initial reg_done = 1'b1; // Initial state is to not be doing anything
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initial reg_done = 1'b1; // Initial state is to not be doing anything
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initial reg_overflow = 1'b0; // And there should be no woverflow present
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initial reg_overflow = 1'b0; // And there should be no woverflow present
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initial reg_sign = 1'b0; // And the sign should be positive
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initial reg_sign = 1'b0; // And the sign should be positive
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assign o_quotient_out[N-2:0] = reg_working_quotient; // The division results
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initial reg_working_quotient = 0;
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initial reg_quotient = 0;
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initial reg_working_dividend = 0;
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initial reg_working_divisor = 0;
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initial reg_count = 0;
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assign o_quotient_out[N-2:0] = reg_quotient[N-2:0]; // The division results
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assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
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assign o_quotient_out[N-1] = reg_sign; // The sign of the quotient
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assign o_complete = reg_done;
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assign o_complete = reg_done;
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assign o_overflow = reg_overflow;
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assign o_overflow = reg_overflow;
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always @( posedge i_clk ) begin
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always @( posedge i_clk ) begin
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if( reg_done && i_start ) begin // This is our startup condition
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if( reg_done && i_start ) begin // This is our startup condition
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// Need to check for a divide by zero right here, I think....
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// Need to check for a divide by zero right here, I think....
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reg_done <= 1'b0; // We're not done
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reg_done <= 1'b0; // We're not done
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reg_count <= N+Q-2; // Set the count
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reg_count <= N+Q-1; // Set the count
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reg_working_quotient <= 0; // Clear out the quotient register
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reg_working_quotient <= 0; // Clear out the quotient register
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reg_working_dividend <= 0; // Clear out the dividend register
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reg_working_dividend <= 0; // Clear out the dividend register
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reg_working_divisor <= 0; // Clear out the divisor register
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reg_working_divisor <= 0; // Clear out the divisor register
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reg_overflow <= 1'b0; // Clear the overflow register
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reg_overflow <= 1'b0; // Clear the overflow register
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| Line 84... |
Line 91... |
end
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end
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//stop condition
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//stop condition
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if(reg_count == 0) begin
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if(reg_count == 0) begin
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reg_done <= 1'b1; // If we're done, it's time to tell the calling process
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reg_done <= 1'b1; // If we're done, it's time to tell the calling process
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reg_quotient <= reg_working_quotient; // Move in our working copy to the outside world
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if (reg_working_quotient[2*N+Q-3:N]>0)
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if (reg_working_quotient[2*N+Q-3:N]>0)
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reg_overflow <= 1'b1;
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reg_overflow <= 1'b1;
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end
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end
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else
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else
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reg_count <= reg_count - 1;
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reg_count <= reg_count - 1;
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