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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Versatile counter ////
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//// ////
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//// Description ////
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//// Versatile counter, a reconfigurable binary, gray or LFSR ////
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//// counter ////
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//// ////
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//// To Do: ////
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//// - add LFSR with more taps ////
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//// ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
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module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
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parameter ADDR_WIDTH = 4;
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parameter ADDR_WIDTH = 4;
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parameter N = ADDR_WIDTH-1;
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parameter N = ADDR_WIDTH-1;
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parameter going_empty = 1'b0;
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parameter going_empty = 1'b0;
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parameter going_full = 1'b1;
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parameter going_full = 1'b1;
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input [N:0] wptr, rptr;
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input [N:0] wptr, rptr;
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output reg fifo_empty, fifo_full;
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output reg fifo_empty;
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output fifo_full;
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input wclk, rclk, rst;
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input wclk, rclk, rst;
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reg direction, direction_set, direction_clr;
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reg direction, direction_set, direction_clr;
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wire async_empty, async_full;
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wire async_empty, async_full;
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reg fifo_full2, fifo_empty2;
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wire fifo_full2;
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reg fifo_empty2;
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// direction_set
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// direction_set
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always @ (wptr[N:N-1] or rptr[N:N-1])
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always @ (wptr[N:N-1] or rptr[N:N-1])
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case ({wptr[N:N-1],rptr[N:N-1]})
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case ({wptr[N:N-1],rptr[N:N-1]})
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{Q1,Q2} : direction_set <= 1'b1;
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{Q1,Q2} : direction_set <= 1'b1;
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{Q4,Q3} : direction_clr <= 1'b1;
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{Q4,Q3} : direction_clr <= 1'b1;
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{Q1,Q4} : direction_clr <= 1'b1;
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{Q1,Q4} : direction_clr <= 1'b1;
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default : direction_clr <= 1'b0;
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default : direction_clr <= 1'b0;
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endcase
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endcase
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`ifndef GENERATE_DIRECTION_AS_LATCH
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dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
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`endif
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`ifdef GENERATE_DIRECTION_AS_LATCH
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always @ (posedge direction_set or posedge direction_clr)
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always @ (posedge direction_set or posedge direction_clr)
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if (direction_clr)
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if (direction_clr)
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direction <= going_empty;
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direction <= going_empty;
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else
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else
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direction <= going_full;
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direction <= going_full;
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`endif
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assign async_empty = (wptr == rptr) && (direction==going_empty);
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assign async_empty = (wptr == rptr) && (direction==going_empty);
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assign async_full = (wptr == rptr) && (direction==going_full);
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assign async_full = (wptr == rptr) && (direction==going_full);
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always @ (posedge wclk or posedge rst or posedge async_full)
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dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
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if (rst)
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dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
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{fifo_full, fifo_full2} <= 2'b00;
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else if (async_full)
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{fifo_full, fifo_full2} <= 2'b11;
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else
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{fifo_full, fifo_full2} <= {fifo_full2, async_full};
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/*
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always @ (posedge wclk or posedge rst or posedge async_full)
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if (rst)
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{fifo_full, fifo_full2} <= 2'b00;
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else if (async_full)
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{fifo_full, fifo_full2} <= 2'b11;
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else
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{fifo_full, fifo_full2} <= {fifo_full2, async_full};
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*/
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always @ (posedge rclk or posedge async_empty)
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always @ (posedge rclk or posedge async_empty)
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if (async_empty)
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if (async_empty)
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{fifo_empty, fifo_empty2} <= 2'b11;
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{fifo_empty, fifo_empty2} <= 2'b11;
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else
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else
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{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
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{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
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