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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Diff between revs 12 and 15

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Rev 12	Rev 15
Line 58...	Line 58...
`else	`else
`always @ (posedge clk)`	`always @ (posedge clk)`
`endif	`endif
`ifdef DW	`ifdef DW
`begin // Port A`	`begin // Port A`
	`q_a <= ram[adr_a];`
`if (we_a)`	`if (we_a)`
`begin`
`ram[adr_a] <= d_a;`	`ram[adr_a] <= d_a;`
`q_a <= d_a;`
`end`
`else`
`q_a <= ram[adr_a];`
`end`	`end`
`else	`else
`if (we_a)`	`if (we_a)`
`ram[adr_a] <= d_a;`	`ram[adr_a] <= d_a;`
`endif	`endif
Line 78...	Line 74...
`else	`else
`always @ (posedge clk)`	`always @ (posedge clk)`
`endif	`endif
`ifdef DW	`ifdef DW
`begin // Port b`	`begin // Port b`
	`q_b <= ram[adr_b];`
`if (we_b)`	`if (we_b)`
`begin`
`ram[adr_b] <= d_b;`	`ram[adr_b] <= d_b;`
`q_b <= d_b;`
`end`
`else`
`q_b <= ram[adr_b];`
`end`	`end`
`else // !`ifdef DW	`else // !`ifdef DW
`adr_b_reg <= adr_b;`	`adr_b_reg <= adr_b;`

`assign q_b = ram[adr_b_reg];`	`assign q_b = ram[adr_b_reg];`

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