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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_dw.v] - Diff between revs 18 and 26
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Rev 26 |
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// true dual port RAM, sync
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`ifdef ACTEL
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`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
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`endif
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module vfifo_dual_port_ram_dc_dw
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module vfifo_dual_port_ram_dc_dw
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(
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(
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d_a,
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d_a,
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q_a,
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q_a,
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adr_a,
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adr_a,
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Line 26... |
input [(DATA_WIDTH-1):0] d_b;
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input [(DATA_WIDTH-1):0] d_b;
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output reg [(DATA_WIDTH-1):0] q_a;
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output reg [(DATA_WIDTH-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(DATA_WIDTH-1):0] q_b;
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reg [(DATA_WIDTH-1):0] q_b;
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reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;
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reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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