URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_sw.v] - Diff between revs 18 and 26

Rev 18	Rev 26
Line 1...	Line 1...
	`// true dual port RAM, sync`

	`ifdef ACTEL
	`define SYN /synthesis syn_ramstyle = "no_rw_check"/
	`endif
`module vfifo_dual_port_ram_dc_sw`	`module vfifo_dual_port_ram_dc_sw`
`(`	`(`
`d_a,`	`d_a,`
`adr_a,`	`adr_a,`
`we_a,`	`we_a,`