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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_sc_dw.v] - Diff between revs 12 and 15
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| Rev 12 |
Rev 15 |
| Line 23... |
Line 23... |
input clk;
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input clk;
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reg [(DATA_WIDTH-1):0] q_b;
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reg [(DATA_WIDTH-1):0] q_b;
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reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
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reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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begin
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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q_a <= d_a;
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end
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else
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q_a <= ram[adr_a];
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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q_b <= ram[adr_b];
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if (we_b)
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if (we_b)
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begin
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ram[adr_b] <= d_b;
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ram[adr_b] <= d_b;
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q_b <= d_b;
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end
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else
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q_b <= ram[adr_b];
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end
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end
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endmodule
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endmodule
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