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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_sc_sw.v] - Diff between revs 26 and 32
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| Rev 26 |
Rev 32 |
| Line 19... |
Line 19... |
input [(ADDR_WIDTH-1):0] adr_b;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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input we_a;
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output [(DATA_WIDTH-1):0] q_b;
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output [(DATA_WIDTH-1):0] q_b;
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input clk;
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input clk;
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reg [(ADDR_WIDTH-1):0] adr_b_reg;
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reg [(ADDR_WIDTH-1):0] adr_b_reg;
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reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;
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reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;
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always @ (posedge clk)
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always @ (posedge clk)
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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always @ (posedge clk)
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always @ (posedge clk)
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adr_b_reg <= adr_b;
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adr_b_reg <= adr_b;
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