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https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_sc_sw.v] - Diff between revs 12 and 17
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| Rev 12 |
Rev 17 |
| Line 5... |
Line 5... |
we_a,
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we_a,
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q_b,
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q_b,
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adr_b,
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adr_b,
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clk
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clk
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);
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);
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parameter DATA_WIDTH = 8;
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parameter DATA_WIDTH = `DATA_WIDTH;
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parameter ADDR_WIDTH = 9;
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parameter ADDR_WIDTH = `ADDR_WIDTH;
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input [(DATA_WIDTH-1):0] d_a;
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input [(DATA_WIDTH-1):0] d_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_a;
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input [(ADDR_WIDTH-1):0] adr_b;
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input [(ADDR_WIDTH-1):0] adr_b;
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input we_a;
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input we_a;
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output [(DATA_WIDTH-1):0] q_b;
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output [(DATA_WIDTH-1):0] q_b;
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input clk;
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input clk;
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reg [(ADDR_WIDTH-1):0] adr_b_reg;
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reg [(ADDR_WIDTH-1):0] adr_b_reg;
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reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ;
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reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;
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always @ (posedge clk)
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always @ (posedge clk)
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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always @ (posedge clk)
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always @ (posedge clk)
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adr_b_reg <= adr_b;
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adr_b_reg <= adr_b;
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