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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [arith.v] - Diff between revs 57 and 58

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Rev 57 Rev 58
Line 242... Line 242...
input [width-1:0] din;
input [width-1:0] din;
output [width-1:0] dout;
output [width-1:0] dout;
input opcode;
input opcode;
 
 
integer i;
integer i;
reg [width/32+4:0] ff1, fl1;
wire [width/32+4:0] ff1, fl1;
 
 
/*
/*
always @(din) begin
always @(din) begin
    ff1 = 0; i = 0;
    ff1 = 0; i = 0;
    while (din[i] == 0 && i < width) begin // complex condition
    while (din[i] == 0 && i < width) begin // complex condition

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