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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [arith.v] - Diff between revs 18 and 40

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//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
 
`ifdef MULTS
// signed multiplication
// signed multiplication
module vl_mults (a,b,p);
`define MODULE mults
 
module `BASE`MODULE (a,b,p);
 
`undef MODULE
parameter operand_a_width = 18;
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_hi = 35;
parameter result_lo = 0;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_a_width-1:0] a;
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    assign bi = b;
    assign bi = b;
    assign result = ai * bi;
    assign result = ai * bi;
    assign p = result[result_hi:result_lo];
    assign p = result[result_hi:result_lo];
 
 
endmodule
endmodule
 
`endif
module vl_mults18x18 (a,b,p);
`ifdef MULTS18X18
 
`define MODULE mults18x18
 
module `BASE`MODULE (a,b,p);
 
`undef MODULE
input [17:0] a,b;
input [17:0] a,b;
output [35:0] p;
output [35:0] p;
vl_mult
vl_mult
    # (.operand_a_width(18), .operand_b_width(18))
    # (.operand_a_width(18), .operand_b_width(18))
    mult0 (.a(a), .b(b), .p(p));
    mult0 (.a(a), .b(b), .p(p));
endmodule
endmodule
 
`endif
 
 
 
`ifdef MULT
 
`define MODULE mult
// unsigned multiplication
// unsigned multiplication
module vl_mult (a,b,p);
module `BASE`MODULE (a,b,p);
 
`undef MODULE
parameter operand_a_width = 18;
parameter operand_a_width = 18;
parameter operand_b_width = 18;
parameter operand_b_width = 18;
parameter result_hi = 35;
parameter result_hi = 35;
parameter result_lo = 0;
parameter result_lo = 0;
input [operand_a_width-1:0] a;
input [operand_a_width-1:0] a;
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    assign result = a * b;
    assign result = a * b;
    assign p = result[result_hi:result_lo];
    assign p = result[result_hi:result_lo];
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef SHIFT_UNIT_32
 
`define MODULE shift_unit_32
// shift unit
// shift unit
// supporting the following shift functions
// supporting the following shift functions
//   SLL
//   SLL
//   SRL
//   SRL
//   SRA
//   SRA
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
`define SHIFT_UNIT_MULT # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7))
module vl_shift_unit_32( din, s, dout, opcode);
module `BASE`MODULE( din, s, dout, opcode);
 
`undef MODULE
input [31:0] din; // data in operand
input [31:0] din; // data in operand
input [4:0] s; // shift operand
input [4:0] s; // shift operand
input [1:0] opcode;
input [1:0] opcode;
output [31:0] dout;
output [31:0] dout;
 
 
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assign sign[3] = din[31] & sra;
assign sign[3] = din[31] & sra;
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[2] = sign[3] & (&din[31:24]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[1] = sign[2] & (&din[23:16]);
assign sign[0] = sign[1] & (&din[15:8]);
assign sign[0] = sign[1] & (&din[15:8]);
vl_mults `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
`define MODULE mults
vl_mults `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
vl_mults `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
vl_mults `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
 
`BASE`MODULE `SHIFT_UNIT_MULT mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
 
`undef MODULE
// second stage is multiplexer based
// second stage is multiplexer based
// shift on byte level
// shift on byte level
 
 
// mux byte 3
// mux byte 3
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
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                     (s[4:3]==2'b01) ? tmp[1] :
                     (s[4:3]==2'b01) ? tmp[1] :
                     (s[4:3]==2'b10) ? tmp[2] :
                     (s[4:3]==2'b10) ? tmp[2] :
                     tmp[3];
                     tmp[3];
 
 
endmodule
endmodule
 
`endif
 
 
 
`ifdef LOGIC_UNIT
// logic unit
// logic unit
// supporting the following logic functions
// supporting the following logic functions
//    a and b
//    a and b
//    a or  b
//    a or  b
//    a xor b
//    a xor b
//    not b
//    not b
module vl_logic_unit( a, b, result, opcode);
`define MODULE logic_unit
 
module `BASE`MODULE( a, b, result, opcode);
 
`undef MODULE
parameter width = 32;
parameter width = 32;
parameter opcode_and = 2'b00;
parameter opcode_and = 2'b00;
parameter opcode_or  = 2'b01;
parameter opcode_or  = 2'b01;
parameter opcode_xor = 2'b10;
parameter opcode_xor = 2'b10;
input [width-1:0] a,b;
input [width-1:0] a,b;
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assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
assign z = (result=={width{1'b0}});
assign z = (result=={width{1'b0}});
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
               (~a[width-1] & ~b[width-1] &  result[width-1]);
               (~a[width-1] & ~b[width-1] &  result[width-1]);
endmodule
endmodule
 
`endif
 
 
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