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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Diff between revs 18 and 21

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Rev 18 Rev 21
Line 69... Line 69...
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
//E2_endif
//E2_endif
endmodule
endmodule
`else
`else
`ifdef ALTERA
`ifdef ALTERA
altera
//altera
`else
`else
 
 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;

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