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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 4 and 5

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Rev 4	Rev 5
Line 38...	Line 38...
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`

`module cnt_shreg_ce ( cke, q, rst, clk);`	`module cnt_shreg_wrap ( q, rst, clk);`

	`parameter length = 4;`
	`output reg [0:length-1] q;`
	`input rst;`
	`input clk;`

	`always @ (posedge clk or posedge rst)`
	`if (rst)`
	`q <= {1'b1,{length-1{1'b0}}};`
	`else`
	`q <= {q[length-1],q[0:length-2]};`

	`endmodule`

	`module cnt_shreg_ce_wrap ( cke, q, rst, clk);`

`parameter length = 4;`	`parameter length = 4;`
`input cke;`	`input cke;`
`output reg [0:length-1] q;`	`output reg [0:length-1] q;`
`input rst;`	`input rst;`
Line 51...	Line 66...
`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`q <= {1'b1,{length-1{1'b0}}};`	`q <= {1'b1,{length-1{1'b0}}};`
`else`	`else`
`if (cke)`	`if (cke)`
`q <= q >> 1;`	`q <= {q[length-1],q[0:length-2]};`

`endmodule`	`endmodule`

`module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);`	`module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);`

`parameter length = 4;`	`parameter length = 4;`
`input cke;`	`input cke, clear;`
`input clear;`
`output reg [0:length-1] q;`	`output reg [0:length-1] q;`
`input rst;`	`input rst;`
`input clk;`	`input clk;`

`always @ (posedge clk or posedge rst)`	`always @ (posedge clk or posedge rst)`
Line 76...	Line 90...
`else`	`else`
`q <= q >> 1;`	`q <= q >> 1;`

`endmodule`	`endmodule`

	`module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);`

	`parameter length = 4;`
	`input cke, clear;`
	`output reg [0:length-1] q;`
	`input rst;`
	`input clk;`

	`always @ (posedge clk or posedge rst)`
	`if (rst)`
	`q <= {1'b1,{length-1{1'b0}}};`
	`else`
	`if (cke)`
	`if (clear)`
	`q <= {1'b1,{length-1{1'b0}}};`
	`else`
	`q <= {q[length-1],q[0:length-2]};`

	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 4 and 5