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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 40 and 104

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Rev 40 Rev 104
Line 78... Line 78...
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
`endif
`endif
 
 
 
`ifdef CNT_SHREG_CLEAR
 
`define MODULE cnt_shreg_clear
 
module `BASE`MODULE ( clear, q, rst, clk);
 
`undef MODULE
 
 
 
   parameter length = 4;
 
   input clear;
 
   output reg [0:length-1] q;
 
   input rst;
 
   input clk;
 
 
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        q <= {1'b1,{length-1{1'b0}}};
 
    else
 
        if (clear)
 
            q <= {1'b1,{length-1{1'b0}}};
 
        else
 
            q <= q >> 1;
 
 
 
endmodule
 
`endif
 
 
`ifdef CNT_SHREG_CE_CLEAR
`ifdef CNT_SHREG_CE_CLEAR
`define MODULE cnt_shreg_ce_clear
`define MODULE cnt_shreg_ce_clear
module `BASE`MODULE ( cke, clear, q, rst, clk);
module `BASE`MODULE ( cke, clear, q, rst, clk);
`undef MODULE
`undef MODULE
 
 

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