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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [counters.v] - Diff between revs 18 and 40

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Rev 18 Rev 40
Line 38... Line 38...
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
 
module vl_cnt_shreg_wrap ( q, rst, clk);
`ifdef CNT_SHREG_WRAP
 
`define MODULE cnt_shreg_wrap
 
module `BASE`MODULE ( q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
Line 52... Line 55...
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        q <= {q[length-1],q[0:length-2]};
        q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
 
`endif
 
 
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
`ifdef CNT_SHREG_CE_WRAP
 
`define MODULE cnt_shreg_ce_wrap
 
module `BASE`MODULE ( cke, q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
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    else
    else
        if (cke)
        if (cke)
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
 
`endif
 
 
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
`ifdef CNT_SHREG_CE_CLEAR
 
`define MODULE cnt_shreg_ce_clear
 
module `BASE`MODULE ( cke, clear, q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
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                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
                q <= q >> 1;
                q <= q >> 1;
 
 
endmodule
endmodule
 
`endif
 
 
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
`ifdef CNT_SHREG_CE_CLEAR_WRAP
 
`define MODULE cnt_shreg_ce_clear_wrap
 
module `BASE`MODULE ( cke, clear, q, rst, clk);
 
`undef MODULE
 
 
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
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                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
 
 
endmodule
endmodule
 
`endif
 
 
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