//=tab Main
|
//=tab Main
|
|
|
//=comment
|
//=comment
|
//=comment Defines base part of module names
|
//=comment Defines base part of module names
|
`define BASE vl_
|
`define BASE vl_
|
|
|
//=comment Defines target technology
|
//=comment Defines target technology
|
//=select
|
//=select
|
//`define GENERIC // GENERIC
|
//`define GENERIC // GENERIC
|
`define ALTERA // ALTERA
|
`define ALTERA // ALTERA
|
//`define ACTEL // ACTEL
|
//`define ACTEL // ACTEL
|
//=end
|
//=end
|
|
|
//=comment
|
//=comment
|
//=comment Generate all modules
|
//=comment Generate all modules
|
//`define ALL
|
`define ALL
|
|
|
|
|
//=comment System Verilog
|
//=comment System Verilog
|
`define SYSTEMVERILOG
|
`define SYSTEMVERILOG
|
|
|
//=tab Clk and reset
|
//=tab Clk and reset
|
|
|
//=comment Global buffer for high fanout signals
|
//=comment Global buffer for high fanout signals
|
`define GBUF
|
//`define GBUF
|
`define SYNC_RST
|
//`define SYNC_RST
|
`define PLL
|
//`define PLL
|
|
|
//=tab registers
|
//=tab registers
|
`define DFF
|
//`define DFF
|
`define DFF_ARRAY
|
//`define DFF_ARRAY
|
`define DFF_CE
|
//`define DFF_CE
|
`define DFF_CE_CLEAR
|
//`define DFF_CE_CLEAR
|
`define DF_CE_SET
|
//`define DF_CE_SET
|
`define SPR
|
//`define SPR
|
`define SRP
|
//`define SRP
|
`define DFF_SR
|
//`define DFF_SR
|
`define LATCH
|
//`define LATCH
|
`define SHREG
|
//`define SHREG
|
`define SHREG_CE
|
//`define SHREG_CE
|
`define DELAY
|
//`define DELAY
|
`define DELAY_EMPTYFLAG
|
//`define DELAY_EMPTYFLAG
|
`define PULSE2TOGGLE
|
//`define PULSE2TOGGLE
|
`define TOGGLE2PULSE
|
//`define TOGGLE2PULSE
|
`define SYNCHRONIZER
|
//`define SYNCHRONIZER
|
`define CDC
|
//`define CDC
|
|
|
//=tab Logic
|
//=tab Logic
|
`define MUX_ANDOR
|
//`define MUX_ANDOR
|
`define MUX2_ANDOR
|
//`define MUX2_ANDOR
|
`define MUX3_ANDOR
|
//`define MUX3_ANDOR
|
`define MUX4_ANDOR
|
//`define MUX4_ANDOR
|
`define MUX5_ANDOR
|
//`define MUX5_ANDOR
|
`define MUX6_ANDOR
|
//`define MUX6_ANDOR
|
`define PARITY
|
//`define PARITY
|
`define SHIFT_UNIT_32
|
//`define SHIFT_UNIT_32
|
`define LOGIC_UNIT
|
//`define LOGIC_UNIT
|
|
|
//=tab
|
//=tab
|
|
|
//=tab IO
|
//=tab IO
|
`define IO_DFF_OE
|
//`define IO_DFF_OE
|
`define O_DFF
|
//`define O_DFF
|
`define O_DDR
|
//`define O_DDR
|
`define O_CLK
|
//`define O_CLK
|
|
|
//=tab Counters
|
//=tab Counters
|
//=comment Binary counters
|
//=comment Binary counters
|
`define CNT_BIN
|
//`define CNT_BIN
|
`define CNT_BIN_CE
|
//`define CNT_BIN_CE
|
`define CNT_BIN_CLEAR
|
//`define CNT_BIN_CLEAR
|
`define CNT_BIN_CE_CLEAR
|
//`define CNT_BIN_CE_CLEAR
|
`define CNT_BIN_CE_CLEAR_L1_L2
|
//`define CNT_BIN_CE_CLEAR_L1_L2
|
`define CNT_BIN_CE_CLEAR_SET_REW
|
//`define CNT_BIN_CE_CLEAR_SET_REW
|
`define CNT_BIN_CE_REW_L1
|
//`define CNT_BIN_CE_REW_L1
|
`define CNT_BIN_CE_REW_ZQ_L1
|
//`define CNT_BIN_CE_REW_ZQ_L1
|
`define CNT_BIN_CE_REW_Q_ZQ_L1
|
//`define CNT_BIN_CE_REW_Q_ZQ_L1
|
//=comment Gray counters
|
//=comment Gray counters
|
`define CNT_GRAY
|
//`define CNT_GRAY
|
`define CNT_GRAY_CE
|
//`define CNT_GRAY_CE
|
`define CNT_GRAY_CE_BIN
|
//`define CNT_GRAY_CE_BIN
|
//=comment LFSR counters
|
//=comment LFSR counters
|
`define CNT_LFSR_ZQ
|
//`define CNT_LFSR_ZQ
|
`define CNT_LFSR_CE
|
//`define CNT_LFSR_CE
|
`define CNT_LFSR_CE_CLEAR_Q
|
//`define CNT_LFSR_CE_CLEAR_Q
|
`define CNT_LFSR_CE_Q
|
//`define CNT_LFSR_CE_Q
|
`define CNT_LFSR_CE_ZQ
|
//`define CNT_LFSR_CE_ZQ
|
`define CNT_LFSR_CE_Q_ZQ
|
//`define CNT_LFSR_CE_Q_ZQ
|
`define CNT_LFSR_CE_REW_L1
|
//`define CNT_LFSR_CE_REW_L1
|
//=comment Shift register based counters
|
//=comment Shift register based counters
|
`define CNT_SHREG_WRAP
|
//`define CNT_SHREG_WRAP
|
`define CNT_SHREG_CLEAR
|
//`define CNT_SHREG_CLEAR
|
`define CNT_SHREG_CE_WRAP
|
//`define CNT_SHREG_CE_WRAP
|
`define CNT_SHREG_CE_CLEAR
|
//`define CNT_SHREG_CE_CLEAR
|
`define CNT_SHREG_CE_CLEAR_WRAP
|
//`define CNT_SHREG_CE_CLEAR_WRAP
|
|
|
//=tab Memories
|
//=tab Memories
|
`define ROM_INIT
|
//`define ROM_INIT
|
`define RAM
|
//`define RAM
|
`define RAM_BE
|
//`define RAM_BE
|
`define DPRAM_1R1W
|
//`define DPRAM_1R1W
|
`define DPRAM_2R1W
|
//`define DPRAM_2R1W
|
`define DPRAM_1R2W
|
//`define DPRAM_1R2W
|
`define DPRAM_2R2W
|
//`define DPRAM_2R2W
|
`define DPRAM_BE_2R2W
|
//`define DPRAM_BE_2R2W
|
`define FIFO_1R1W_FILL_LEVEL_SYNC
|
//`define FIFO_1R1W_FILL_LEVEL_SYNC
|
`define FIFO_2R2W_SYNC_SIMPLEX
|
//`define FIFO_2R2W_SYNC_SIMPLEX
|
`define FIFO_CMP_ASYNC
|
//`define FIFO_CMP_ASYNC
|
`define FIFO_1R1W_ASYNC
|
//`define FIFO_1R1W_ASYNC
|
`define FIFO_2R2W_ASYNC
|
//`define FIFO_2R2W_ASYNC
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
//`define FIFO_2R2W_ASYNC_SIMPLEX
|
`define REG_FILE
|
//`define REG_FILE
|
|
|
//=tab Wishbone
|
//=tab Wishbone
|
`define WB3AVALON_BRIDGE
|
//`define WB3AVALON_BRIDGE
|
`define WB3WB3_BRIDGE
|
//`define WB3WB3_BRIDGE
|
`define WB3_ARBITER_TYPE1
|
//`define WB3_ARBITER_TYPE1
|
`define WB_ADR_INC
|
//`define WB_ADR_INC
|
`define WB_RAM
|
//`define WB_RAM
|
`define WB_SHADOW_RAM
|
//`define WB_SHADOW_RAM
|
`define WB_B4_ROM
|
//`define WB_B4_ROM
|
`define WB_BOOT_ROM
|
//`define WB_BOOT_ROM
|
`define WB_DPRAM
|
//`define WB_DPRAM
|
`define WB_CACHE
|
//`define WB_CACHE
|
`define WB_AVALON_BRIDGE
|
//`define WB_AVALON_BRIDGE
|
`define WB_AVALON_MEM_CACHE
|
//`define WB_AVALON_MEM_CACHE
|
`define WB_SDR_SDRAM_CTRL
|
//`define WB_SDR_SDRAM_CTRL
|
|
|
//=tab Arithmetic
|
//=tab Arithmetic
|
`define MULTS
|
//`define MULTS
|
`define MULTS18X18
|
//`define MULTS18X18
|
`define MULT
|
//`define MULT
|
|
//`define ARITH_UNIT
|
|
//`define COUNT_UNIT
|
|
//`define EXT_UNIT
|
|
|
///////////////////////////////////////
|
///////////////////////////////////////
|
// dependencies
|
// dependencies
|
///////////////////////////////////////
|
///////////////////////////////////////
|
|
|
`ifdef PLL
|
`ifdef PLL
|
`ifndef SYNC_RST
|
`ifndef SYNC_RST
|
`define SYNC_RST
|
`define SYNC_RST
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef SYNC_RST
|
`ifdef SYNC_RST
|
`ifndef GBUF
|
`ifndef GBUF
|
`define GBUF
|
`define GBUF
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB_SDR_SDRAM_CTRL
|
`ifdef WB_SDR_SDRAM_CTRL
|
`ifndef WB_SHADOW_RAM
|
`ifndef WB_SHADOW_RAM
|
`define WB_SHADOW_RAM
|
`define WB_SHADOW_RAM
|
`endif
|
`endif
|
`ifndef WB_CACHE
|
`ifndef WB_CACHE
|
`define WB_CACHE
|
`define WB_CACHE
|
`endif
|
`endif
|
`ifndef WB_SDR_SDRAM
|
`ifndef WB_SDR_SDRAM
|
`define WB_SDR_SDRAM
|
`define WB_SDR_SDRAM
|
`endif
|
`endif
|
`ifndef IO_DFF_OE
|
`ifndef IO_DFF_OE
|
`define IO_DFF_OE
|
`define IO_DFF_OE
|
`endif
|
`endif
|
`ifndef O_DFF
|
`ifndef O_DFF
|
`define O_DFF
|
`define O_DFF
|
`endif
|
`endif
|
`ifndef O_CLK
|
`ifndef O_CLK
|
`define O_CLK
|
`define O_CLK
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB_SDR_SDRAM
|
`ifdef WB_SDR_SDRAM
|
`ifndef CNT_SHREG_CLEAR
|
`ifndef CNT_SHREG_CLEAR
|
`define CNT_SHREG_CLEAR
|
`define CNT_SHREG_CLEAR
|
`endif
|
`endif
|
`ifndef CNT_LFSR_ZQ
|
`ifndef CNT_LFSR_ZQ
|
`define CNT_LFSR_ZQ
|
`define CNT_LFSR_ZQ
|
`endif
|
`endif
|
`ifndef DELAY_EMPTYFLAG
|
`ifndef DELAY_EMPTYFLAG
|
`define DELAY_EMPTYFLAG
|
`define DELAY_EMPTYFLAG
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB_DPRAM
|
`ifdef WB_DPRAM
|
`ifndef WB_ADR_INC
|
`ifndef WB_ADR_INC
|
`define WB_ADR_INC
|
`define WB_ADR_INC
|
`endif
|
`endif
|
`ifndef DPRAM_BE_2R2W
|
`ifndef DPRAM_BE_2R2W
|
`define DPRAM_BE_2R2W
|
`define DPRAM_BE_2R2W
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB3_ARBITER_TYPE1
|
`ifdef WB3_ARBITER_TYPE1
|
`ifndef SPR
|
`ifndef SPR
|
`define SPR
|
`define SPR
|
`endif
|
`endif
|
`ifndef MUX_ANDOR
|
`ifndef MUX_ANDOR
|
`define MUX_ANDOR
|
`define MUX_ANDOR
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB3AVALON_BRIDGE
|
`ifdef WB3AVALON_BRIDGE
|
`ifndef WB3WB3_BRIDGE
|
`ifndef WB3WB3_BRIDGE
|
`define WB3WB3_BRIDGE
|
`define WB3WB3_BRIDGE
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB3WB3_BRIDGE
|
`ifdef WB3WB3_BRIDGE
|
`ifndef CNT_SHREG_CE_CLEAR
|
`ifndef CNT_SHREG_CE_CLEAR
|
`define CNT_SHREG_CE_CLEAR
|
`define CNT_SHREG_CE_CLEAR
|
`endif
|
`endif
|
`ifndef DFF
|
`ifndef DFF
|
`define DFF
|
`define DFF
|
`endif
|
`endif
|
`ifndef DFF_CE
|
`ifndef DFF_CE
|
`define DFF_CE
|
`define DFF_CE
|
`endif
|
`endif
|
`ifndef CNT_SHREG_CE_CLEAR
|
`ifndef CNT_SHREG_CE_CLEAR
|
`define CNT_SHREG_CE_CLEAR
|
`define CNT_SHREG_CE_CLEAR
|
`endif
|
`endif
|
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
|
`ifndef FIFO_2R2W_ASYNC_SIMPLEX
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
`define FIFO_2R2W_ASYNC_SIMPLEX
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
|
|
`ifdef WB_AVALON_MEM_CACHE
|
`ifdef WB_AVALON_MEM_CACHE
|
`ifndef WB_SHADOW_RAM
|
`ifndef WB_SHADOW_RAM
|
`define WB_SHADOW_RAM
|
`define WB_SHADOW_RAM
|
`endif
|
`endif
|
`ifndef WB_CACHE
|
`ifndef WB_CACHE
|
`define WB_CACHE
|
`define WB_CACHE
|
`endif
|
`endif
|
`ifndef WB_AVALON_BRIDGE
|
`ifndef WB_AVALON_BRIDGE
|
`define WB_AVALON_BRIDGE
|
`define WB_AVALON_BRIDGE
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB_CACHE
|
`ifdef WB_CACHE
|
`ifndef RAM
|
`ifndef RAM
|
`define RAM
|
`define RAM
|
`endif
|
`endif
|
`ifndef WB_ADR_INC
|
`ifndef WB_ADR_INC
|
`define WB_ADR_INC
|
`define WB_ADR_INC
|
`endif
|
`endif
|
`ifndef DPRAM_1R1W
|
`ifndef DPRAM_1R1W
|
`define DPRAM_1R1W
|
`define DPRAM_1R1W
|
`endif
|
`endif
|
`ifndef DPRAM_1R2W
|
`ifndef DPRAM_1R2W
|
`define DPRAM_1R2W
|
`define DPRAM_1R2W
|
`endif
|
`endif
|
`ifndef DPRAM_BE_2R2W
|
`ifndef DPRAM_BE_2R2W
|
`define DPRAM_BE_2R2W
|
`define DPRAM_BE_2R2W
|
`endif
|
`endif
|
`ifndef CDC
|
`ifndef CDC
|
`define CDC
|
`define CDC
|
`endif
|
`endif
|
`ifndef O_DFF
|
`ifndef O_DFF
|
`define O_DFF
|
`define O_DFF
|
`endif
|
`endif
|
`ifndef O_CLK
|
`ifndef O_CLK
|
`define O_CLK
|
`define O_CLK
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB_SHADOW_RAM
|
`ifdef WB_SHADOW_RAM
|
`ifndef WB_RAM
|
`ifndef WB_RAM
|
`define WB_RAM
|
`define WB_RAM
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef WB_RAM
|
`ifdef WB_RAM
|
`ifndef WB_ADR_INC
|
`ifndef WB_ADR_INC
|
`define WB_ADR_INC
|
`define WB_ADR_INC
|
`endif
|
`endif
|
`ifndef RAM_BE
|
`ifndef RAM_BE
|
`define RAM_BE
|
`define RAM_BE
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MULTS18X18
|
`ifdef MULTS18X18
|
`ifndef MULTS
|
`ifndef MULTS
|
`define MULTS
|
`define MULTS
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef SHIFT_UNIT_32
|
`ifdef SHIFT_UNIT_32
|
`ifndef MULTS
|
`ifndef MULTS
|
`define MULTS
|
`define MULTS
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MUX2_ANDOR
|
`ifdef MUX2_ANDOR
|
`ifndef MUX_ANDOR
|
`ifndef MUX_ANDOR
|
`define MUX_ANDOR
|
`define MUX_ANDOR
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MUX3_ANDOR
|
`ifdef MUX3_ANDOR
|
`ifndef MUX_ANDOR
|
`ifndef MUX_ANDOR
|
`define MUX_ANDOR
|
`define MUX_ANDOR
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MUX4_ANDOR
|
`ifdef MUX4_ANDOR
|
`ifndef MUX_ANDOR
|
`ifndef MUX_ANDOR
|
`define MUX_ANDOR
|
`define MUX_ANDOR
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MUX5_ANDOR
|
`ifdef MUX5_ANDOR
|
`ifndef MUX_ANDOR
|
`ifndef MUX_ANDOR
|
`define MUX_ANDOR
|
`define MUX_ANDOR
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef MUX6_ANDOR
|
`ifdef MUX6_ANDOR
|
`ifndef MUX_ANDOR
|
`ifndef MUX_ANDOR
|
`define MUX_ANDOR
|
`define MUX_ANDOR
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
`ifndef CNT_BIN_CE
|
`ifndef CNT_BIN_CE
|
`define CNT_BIN_CE
|
`define CNT_BIN_CE
|
`endif
|
`endif
|
`ifndef DPRAM_1R1W
|
`ifndef DPRAM_1R1W
|
`define DPRAM_1R1W
|
`define DPRAM_1R1W
|
`endif
|
`endif
|
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
|
`ifndef CNT_BIN_CE_REW_Q_ZQ_L1
|
`define CNT_BIN_CE_REW_Q_ZQ_L1
|
`define CNT_BIN_CE_REW_Q_ZQ_L1
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
`ifdef FIFO_1R1W_FILL_LEVEL_SYNC
|
`ifndef CNT_LFSR_CE
|
`ifndef CNT_LFSR_CE
|
`define CNT_LFSR_CE
|
`define CNT_LFSR_CE
|
`endif
|
`endif
|
`ifndef DPRAM_2R2W
|
`ifndef DPRAM_2R2W
|
`define DPRAM_2R2W
|
`define DPRAM_2R2W
|
`endif
|
`endif
|
`ifndef CNT_BIN_CE_REW_ZQ_L1
|
`ifndef CNT_BIN_CE_REW_ZQ_L1
|
`define CNT_BIN_CE_REW_ZQ_L1
|
`define CNT_BIN_CE_REW_ZQ_L1
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
|
`ifdef FIFO_2R2W_ASYNC_SIMPLEX
|
`ifndef CNT_GRAY_CE_BIN
|
`ifndef CNT_GRAY_CE_BIN
|
`define CNT_GRAY_CE_BIN
|
`define CNT_GRAY_CE_BIN
|
`endif
|
`endif
|
`ifndef DPRAM_2R2W
|
`ifndef DPRAM_2R2W
|
`define DPRAM_2R2W
|
`define DPRAM_2R2W
|
`endif
|
`endif
|
`ifndef FIFO_CMP_ASYNC
|
`ifndef FIFO_CMP_ASYNC
|
`define FIFO_CMP_ASYNC
|
`define FIFO_CMP_ASYNC
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FIFO_2R2W_ASYNC
|
`ifdef FIFO_2R2W_ASYNC
|
`ifndef FIFO_1R1W_ASYNC
|
`ifndef FIFO_1R1W_ASYNC
|
`define FIFO_1R1W_ASYNC
|
`define FIFO_1R1W_ASYNC
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FIFO_1R1W_ASYNC
|
`ifdef FIFO_1R1W_ASYNC
|
`ifndef CNT_GRAY_CE_BIN
|
`ifndef CNT_GRAY_CE_BIN
|
`define CNT_GRAY_CE_BIN
|
`define CNT_GRAY_CE_BIN
|
`endif
|
`endif
|
`ifndef DPRAM_1R1W
|
`ifndef DPRAM_1R1W
|
`define DPRAM_1R1W
|
`define DPRAM_1R1W
|
`endif
|
`endif
|
`ifndef FIFO_CMP_ASYNC
|
`ifndef FIFO_CMP_ASYNC
|
`define FIFO_CMP_ASYNC
|
`define FIFO_CMP_ASYNC
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef FIFO_CMP_ASYNC
|
`ifdef FIFO_CMP_ASYNC
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`ifndef DFF_SR
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`ifndef DFF_SR
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`define DFF_SR
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`define DFF_SR
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`endif
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`endif
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`ifndef DFF
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`ifndef DFF
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`define DFF
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`define DFF
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`endif
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`endif
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`endif
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`endif
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|
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`ifdef REG_FILE
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`ifdef REG_FILE
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`ifndef DPRAM_1R1W
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`ifndef DPRAM_1R1W
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`define DPRAM_1R1W
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`define DPRAM_1R1W
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`endif
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`endif
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`endif
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`endif
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|
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`ifdef CDC
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`ifdef CDC
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`ifndef PULSE2TOGGLE
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`ifndef PULSE2TOGGLE
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`define PULSE2TOGGLE
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`define PULSE2TOGGLE
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`endif
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`endif
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`ifndef TOGGLE2PULSE
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`ifndef TOGGLE2PULSE
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`define TOGGLE2PULSE
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`define TOGGLE2PULSE
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`endif
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`endif
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`ifndef SYNCHRONIZER
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`ifndef SYNCHRONIZER
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`define SYNCHRONIZER
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`define SYNCHRONIZER
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`endif
|
`endif
|
`endif
|
`endif
|
|
|
`ifdef O_CLK
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`ifdef O_CLK
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`ifndef O_DDR
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`ifndef O_DDR
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`define O_DDR
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`define O_DDR
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`endif
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`endif
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`endif
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`endif
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|
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// size to width
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// size to width
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`define SIZE2WIDTH_EXPR
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//`define SIZE2WIDTH_EXPR
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No newline at end of file
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No newline at end of file
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