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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 98 and 100

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Rev 98 Rev 100
Line 45... Line 45...
`define ROM_INIT
`define ROM_INIT
`define RAM
`define RAM
`define RAM_BE
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_1R1W
`define DPRAM_2R1W
`define DPRAM_2R1W
 
`define DPRAM_1R2W
`define DPRAM_2R2W
`define DPRAM_2R2W
`define DPRAM_BE_2R2W
`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC
`define FIFO_CMP_ASYNC
Line 159... Line 160...
 `define RAM
 `define RAM
 `endif
 `endif
 `ifndef WB_ADR_INC
 `ifndef WB_ADR_INC
 `define WB_ADR_INC
 `define WB_ADR_INC
 `endif
 `endif
 `ifndef dpram_be_2r2w
`ifndef DPRAM_1R1W
 
`define DPRAM_1R1W
 
`endif
 
`ifndef DPRAM_1R2W
 
`define DPRAM_1R2W
 
`endif
 
`ifndef DPRAM_BE_2R2W
 `define DPRAM_BE_2R2W
 `define DPRAM_BE_2R2W
 `endif
 `endif
 `ifndef CDC
 `ifndef CDC
 `define CDC
 `define CDC
 `endif
 `endif
Line 291... Line 298...
`define SYNCHRONIZER
`define SYNCHRONIZER
`endif
`endif
`endif
`endif
 
 
// size to width
// size to width
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==1) ? 0 : (`SIZE2WIDTH==2) ? 1 : (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;
 
 
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