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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 101 and 103

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Rev 101	Rev 103
Line 79...	Line 79...
`define WB3AVALON_BRIDGE	`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE	`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1	`define WB3_ARBITER_TYPE1
`define WB_ADR_INC	`define WB_ADR_INC
`define WB_RAM	`define WB_RAM
	`define WB_SHADOW_RAM
`define WB_B4_ROM	`define WB_B4_ROM
`define WB_BOOT_ROM	`define WB_BOOT_ROM
`define WB_DPRAM	`define WB_DPRAM
`define WB_CACHE	`define WB_CACHE
	`define WB_AVALON_BRIDGE
	`define WB_AVALON_MEM_CACHE

`define IO_DFF_OE	`define IO_DFF_OE
`define O_DFF	`define O_DFF

`endif	`endif
Line 152...	Line 155...
`ifndef FIFO_2R2W_ASYNC_SIMPLEX	`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX	`define FIFO_2R2W_ASYNC_SIMPLEX
`endif	`endif
`endif	`endif


	`ifdef WB_AVALON_MEM_CACHE
	`ifndef WB_SHADOW_RAM
	`define WB_SHADOW_RAM
	`endif
	`ifndef WB_CACHE
	`define WB_CACHE
	`endif
	`ifndef WB_AVALON_BRIDGE
	`define WB_AVALON_BRIDGE
	`endif
	`endif

`ifdef WB_CACHE	`ifdef WB_CACHE
`ifndef RAM	`ifndef RAM
`define RAM	`define RAM
`endif	`endif
`ifndef WB_ADR_INC	`ifndef WB_ADR_INC
Line 173...	Line 189...
`ifndef CDC	`ifndef CDC
`define CDC	`define CDC
`endif	`endif
`endif	`endif

	`ifdef WB_SHADOW_RAM
	`ifndef WB_RAM
	`define WB_RAM
	`endif
	`endif

	`ifdef WB_RAM
	`ifndef WB_ADR_INC
	`define WB_ADR_INC
	`endif
	`endif

`ifdef MULTS18X18	`ifdef MULTS18X18
`ifndef MULTS	`ifndef MULTS
`define MULTS	`define MULTS
`endif	`endif
`endif	`endif

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