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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 42 and 43

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Rev 42 Rev 43
Line 23... Line 23...
`define MUX2_ANDOR
`define MUX2_ANDOR
`define MUX3_ANDOR
`define MUX3_ANDOR
`define MUX4_ANDOR
`define MUX4_ANDOR
`define MUX5_ANDOR
`define MUX5_ANDOR
`define MUX6_ANDOR
`define MUX6_ANDOR
 
`define PARITY
 
 
`define ROM_INIT
`define ROM_INIT
`define RAM
`define RAM
`define RAM_BE
`define RAM_BE
`define DPRAM_1R1W
`define DPRAM_1R1W

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