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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 43 and 44

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Rev 43 Rev 44
Line 1... Line 1...
`ifndef BASE
`ifndef BASE
`define BASE vl_
`define BASE vl_
`endif
`endif
 
 
 
`ifdef ACTEL
 
`define SYN_KEEP /*synthesis syn_keep = 1*/
 
`endif
 
 
`ifdef ALL
`ifdef ALL
 
 
`define GBUF
`define GBUF
`define SYNC_RST
`define SYNC_RST
`define PLL
`define PLL
Line 57... Line 61...
`define WB3WB3_BRIDGE
`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1
`define WB3_ARBITER_TYPE1
`define WB_BOOT_ROM
`define WB_BOOT_ROM
`define WB_DPRAM
`define WB_DPRAM
 
 
 
`define IO_DFF_OE
 
`define O_DFF
 
 
`endif
`endif
 
 
`ifdef PLL
`ifdef PLL
`ifndef SYNC_RST
`ifndef SYNC_RST
`define SYNC_RST
`define SYNC_RST

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