URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 62 and 75

Rev 62	Rev 75
Line 39...	Line 39...
`define RAM	`define RAM
`define RAM_BE	`define RAM_BE
`define DPRAM_1R1W	`define DPRAM_1R1W
`define DPRAM_2R1W	`define DPRAM_2R1W
`define DPRAM_2R2W	`define DPRAM_2R2W
	`define DPRAM_BE_2R2W
`define FIFO_1R1W_FILL_LEVEL_SYNC	`define FIFO_1R1W_FILL_LEVEL_SYNC
`define FIFO_2R2W_SYNC_SIMPLEX	`define FIFO_2R2W_SYNC_SIMPLEX
`define FIFO_CMP_ASYNC	`define FIFO_CMP_ASYNC
`define FIFO_1R1W_ASYNC	`define FIFO_1R1W_ASYNC
`define FIFO_2R2W_ASYNC	`define FIFO_2R2W_ASYNC
Line 61...	Line 62...
`define SHREG	`define SHREG
`define SHREG_CE	`define SHREG_CE
`define DELAY	`define DELAY
`define DELAY_EMPTYFLAG	`define DELAY_EMPTYFLAG

	`define WB3AVALON_BRIDGE
`define WB3WB3_BRIDGE	`define WB3WB3_BRIDGE
`define WB3_ARBITER_TYPE1	`define WB3_ARBITER_TYPE1
`define WB_B3_RAM_BE	`define WB_B3_RAM_BE
`define WB_B4_RAM_BE	`define WB_B4_RAM_BE
`define WB_B4_ROM	`define WB_B4_ROM