URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Diff between revs 94 and 97

Rev 94	Rev 97
Line 75...	Line 75...
`define WB_B3_RAM_BE	`define WB_B3_RAM_BE
`define WB_B4_RAM_BE	`define WB_B4_RAM_BE
`define WB_B4_ROM	`define WB_B4_ROM
`define WB_BOOT_ROM	`define WB_BOOT_ROM
`define WB_DPRAM	`define WB_DPRAM
	`define WBB3_WBB4_CACHE

`define IO_DFF_OE	`define IO_DFF_OE
`define O_DFF	`define O_DFF

`endif	`endif
Line 156...	Line 157...
`ifndef FIFO_2R2W_ASYNC_SIMPLEX	`ifndef FIFO_2R2W_ASYNC_SIMPLEX
`define FIFO_2R2W_ASYNC_SIMPLEX	`define FIFO_2R2W_ASYNC_SIMPLEX
`endif	`endif
`endif	`endif

	`ifdef WBB3_WBB4_CACHE
	`ifndef RAM
	`define RAM
	`endif
	`ifndef WB_ADR_INC
	`define WB_ADR_INC
	`endif
	`ifndef dpram_be_2r2w
	`define DPRAM_BE_2R2W
	`endif
	`endif

`ifdef MULTS18X18	`ifdef MULTS18X18
`ifndef MULTS	`ifndef MULTS
`define MULTS	`define MULTS
`endif	`endif
`endif	`endif
Line 267...	Line 280...
`ifndef DPRAM_1R1W	`ifndef DPRAM_1R1W
`define DPRAM_1R1W	`define DPRAM_1R1W
`endif	`endif
`endif	`endif

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	`// size to width`
	`define SIZE2WIDTH_EXPR = (`SIZE2WIDTH==4) ? 2 : (`SIZE2WIDTH==8) ? 3 : (`SIZE2WIDTH==16) ? 4 : (`SIZE2WIDTH==32) ? 5 : (`SIZE2WIDTH==64) ? 6 : (`SIZE2WIDTH==128) ? 7 : 8;

`No newline at end of file`	`No newline at end of file`