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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [io.v] - Diff between revs 136 and 139

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Rev 136 Rev 139
Line 70... Line 70...
`timescale 1ns/1ns
`timescale 1ns/1ns
`define MODULE io_dff_oe
`define MODULE io_dff_oe
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
module `BASE`MODULE ( d_i, d_o, oe, io_pad, clk, rst);
`undef MODULE
`undef MODULE
parameter width = 1;
parameter width = 1;
 
parameter reset_value = 1'b0;
input  [width-1:0] d_o;
input  [width-1:0] d_o;
output reg [width-1:0] d_i;
output reg [width-1:0] d_i;
input oe;
input oe;
inout [width-1:0] io_pad;
inout [width-1:0] io_pad;
input clk, rst;
input clk, rst;
Line 89... Line 90...
        oe_q[i] <= 1'b0;
        oe_q[i] <= 1'b0;
    else
    else
        oe_q[i] <= oe_d[i];
        oe_q[i] <= oe_d[i];
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        d_o_q[i] <= 1'b0;
        d_o_q[i] <= reset_value;
    else
    else
        d_o_q[i] <= d_o[i];
        d_o_q[i] <= d_o[i];
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        d_i[i] <= 1'b0;
        d_i[i] <= reset_value;
    else
    else
        d_i[i] <= io_pad[i];
        d_i[i] <= io_pad[i];
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
end
end
endgenerate
endgenerate

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