//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Logic functions ////
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//// Logic functions ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Logic functions such as multiplexers ////
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//// Logic functions such as multiplexers ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - ////
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//// - ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ORSoC AB ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module vl_mux2_andor ( a1, a0, sel, dout);
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parameter width = 32;
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parameter nr_of_ports = 2;
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input [width-1:0] a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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// or
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assign dout = tmp[1] | tmp[0];
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endmodule
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module vl_mux3_andor ( a2, a1, a0, sel, dout);
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parameter width = 32;
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parameter nr_of_ports = 3;
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input [width-1:0] a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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// or
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assign dout = tmp[2] | tmp[1] | tmp[0];
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endmodule
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module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
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module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
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parameter width = 32;
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parameter width = 32;
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parameter nr_of_ports = 4;
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parameter nr_of_ports = 4;
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input [width-1:0] a3, a2, a1, a0;
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input [width-1:0] a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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wire [width-1:0] tmp [nr_of_ports-1:0];
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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integer i;
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// and
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[3] = {width{sel[3]}} & a3;
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assign tmp[3] = {width{sel[3]}} & a3;
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// or
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// or
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assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
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assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
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endmodule
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endmodule
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module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
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module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
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parameter width = 32;
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parameter width = 32;
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parameter nr_of_ports = 5;
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parameter nr_of_ports = 5;
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input [width-1:0] a4, a3, a2, a1, a0;
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input [width-1:0] a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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wire [width-1:0] tmp [nr_of_ports-1:0];
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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integer i;
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// and
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[3] = {width{sel[3]}} & a3;
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assign tmp[3] = {width{sel[3]}} & a3;
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assign tmp[4] = {width{sel[4]}} & a4;
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assign tmp[4] = {width{sel[4]}} & a4;
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// or
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// or
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assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
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assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
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endmodule
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endmodule
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module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
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module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
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parameter width = 32;
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parameter width = 32;
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parameter nr_of_ports = 6;
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parameter nr_of_ports = 6;
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input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [width-1:0] a5, a4, a3, a2, a1, a0;
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input [nr_of_ports-1:0] sel;
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input [nr_of_ports-1:0] sel;
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output [width-1:0] dout;
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output [width-1:0] dout;
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wire [width-1:0] tmp [nr_of_ports-1:0];
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wire [width-1:0] tmp [nr_of_ports-1:0];
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integer i;
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integer i;
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// and
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// and
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[0] = {width{sel[0]}} & a0;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[1] = {width{sel[1]}} & a1;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[2] = {width{sel[2]}} & a2;
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assign tmp[3] = {width{sel[3]}} & a3;
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assign tmp[3] = {width{sel[3]}} & a3;
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assign tmp[4] = {width{sel[4]}} & a4;
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assign tmp[4] = {width{sel[4]}} & a4;
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assign tmp[5] = {width{sel[5]}} & a5;
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assign tmp[5] = {width{sel[5]}} & a5;
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// or
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// or
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assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
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assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
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endmodule
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endmodule
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