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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Diff between revs 40 and 42

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Rev 40 Rev 42
Line 54... Line 54...
integer i,j;
integer i,j;
 
 
always @ (a, sel)
always @ (a, sel)
begin
begin
    dout = a[width-1:0] & {width{sel[0]}};
    dout = a[width-1:0] & {width{sel[0]}};
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
    for (i=1;i<nr_of_ports;i=i+1)
        for (j=0;j<32;j=j+1)
        for (j=0;j<width;j=j+1)
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
end
end
 
 
endmodule
endmodule
`endif
`endif
 
 

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