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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Diff between revs 43 and 44

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Rev 43 Rev 44
Line 190... Line 190...
parameter chunk_size = 8;
parameter chunk_size = 8;
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
input [word_size-1:0] data;
input [word_size-1:0] data;
input [word_size/chunk_size-1:0] parity;
input [word_size/chunk_size-1:0] parity;
output parity_error;
output parity_error;
reg [chunk_size-1:0] error_flag;
reg [word_size/chunk_size-1:0] error_flag;
integer i,j;
integer i,j;
always @ (data or parity)
always @ (data or parity)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    error_flag[i] = parity[i] ^ parity_type;
    error_flag[i] = parity[i] ^ parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin

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