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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Diff between revs 44 and 46

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Rev 44 Rev 46
Line 176... Line 176...
integer i,j;
integer i,j;
always @ (data)
always @ (data)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    parity[i] = parity_type;
    parity[i] = parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin
        parity[i] = data[i+j] ^ parity[i];
        parity[i] = data[i*chunk_size+j] ^ parity[i];
    end
    end
end
end
endmodule
endmodule
 
 
`define MODULE parity_check
`define MODULE parity_check
Line 196... Line 196...
integer i,j;
integer i,j;
always @ (data or parity)
always @ (data or parity)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    error_flag[i] = parity[i] ^ parity_type;
    error_flag[i] = parity[i] ^ parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin
        error_flag[i] = data[i+j] ^ error_flag[i];
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
    end
    end
end
end
assign parity_error = |error_flag;
assign parity_error = |error_flag;
endmodule
endmodule
 
 

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