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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 119 and 124

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Rev 119 Rev 124
Line 436... Line 436...
`undef MODULE
`undef MODULE
 
 
   parameter a_data_width = 32;
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter a_addr_width = 8;
   parameter b_data_width = 64; //a_data_width;
   parameter b_data_width = 64; //a_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
 
   localparam b_addr_width =
 
        (a_data_width==b_data_width) ? aw_m :
 
        (a_data_width==b_data_width*2) ? aw_m+1 :
 
        (a_data_width==b_data_width*4) ? aw_m+2 :
 
        (a_data_width==b_data_width*8) ? aw_m+3 :
 
        (a_data_width==b_data_width*16) ? aw_m+4 :
 
        (a_data_width==b_data_width*32) ? aw_m+5 :
 
        (a_data_width==b_data_width/2) ? aw_m-1 :
 
        (a_data_width==b_data_width/4) ? aw_m-2 :
 
        (a_data_width==b_data_width/8) ? aw_m-3 :
 
        (a_data_width==b_data_width/16) ? aw_m-4 :
 
        (a_data_width==b_data_width/32) ? aw_m-5 : 0;
 
 
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
 
 
   parameter memory_init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";

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