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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 137 and 141

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Rev 137 Rev 141
Line 473... Line 473...
 
 
    generate
    generate
    if (debug==1) begin : debug_we
    if (debug==1) begin : debug_we
        always @ (posedge clk_a)
        always @ (posedge clk_a)
        if (we_a)
        if (we_a)
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
            $display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
        always @ (posedge clk_b)
        always @ (posedge clk_b)
        if (we_b)
        if (we_b)
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
            $display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
    end
    end
    endgenerate
    endgenerate
 
 
 
 
//E2_ifdef SYSTEMVERILOG
//E2_ifdef SYSTEMVERILOG

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