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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 14 and 18

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Rev 14 Rev 18
Line 326... Line 326...
         {Q1,Q4} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
         default : direction_clr <= 1'b0;
       endcase
       endcase
 
 
`ifndef GENERATE_DIRECTION_AS_LATCH
`ifndef GENERATE_DIRECTION_AS_LATCH
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
`endif
 
 
`ifdef GENERATE_DIRECTION_AS_LATCH
`ifdef GENERATE_DIRECTION_AS_LATCH
   always @ (posedge direction_set or posedge direction_clr)
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
     if (direction_clr)
Line 340... Line 340...
`endif
`endif
 
 
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
   assign async_full  = (wptr == rptr) && (direction==going_full);
 
 
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
 
/*
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
       {fifo_full, fifo_full2} <= 2'b00;
Line 357... Line 357...
/*   always @ (posedge rclk or posedge async_empty)
/*   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
 
 
endmodule // async_comp
endmodule // async_comp
 
 
module vl_fifo_1r1w_async (
module vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
Line 390... Line 390...
vl_fifo_1r1w_async (
vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
 
 
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
 
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
 
 
vl_dpram_1r1w
vl_dpram_1r1w
    # (.data_width(data_width), .addr_width(addr_width))
    # (.data_width(data_width), .addr_width(addr_width))
Line 496... Line 496...
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
 
 
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
 
 
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
 
 
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
 
 
cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
 
 
// mux read or write adr to DPRAM
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};

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