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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 18 and 21

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Rev 18 Rev 21
Line 384... Line 384...
output                  fifo_empty;
output                  fifo_empty;
input                   rd_clk;
input                   rd_clk;
input                   rd_rst;
input                   rd_rst;
 
 
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
 
/*
vl_fifo_1r1w_async (
vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
 
*/
vl_cnt_gray_ce_bin
vl_cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
 
 
vl_cnt_gray_ce_bin
vl_cnt_gray_ce_bin

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