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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 40 and 48

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Line 62... Line 62...
     q <= rom[adr];
     q <= rom[adr];
 
 
endmodule
endmodule
`endif
`endif
 
 
/*
 
module vl_rom ( adr, q, clk);
 
 
 
parameter data_width = 32;
 
parameter addr_width = 4;
 
 
 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
 
    {32'h18000000},
 
    {32'hA8200000},
 
    {32'hA8200000},
 
    {32'hA8200000},
 
    {32'h44003000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000}};
 
 
 
input [addr_width-1:0] adr;
 
output reg [data_width-1:0] q;
 
input clk;
 
 
 
always @ (posedge clk)
 
    q <= data[adr];
 
 
 
endmodule
 
*/
 
 
 
`ifdef RAM
`ifdef RAM
`define MODULE ram
`define MODULE ram
// Single port RAM
// Single port RAM
module `BASE`MODULE ( d, adr, we, q, clk);
module `BASE`MODULE ( d, adr, we, q, clk);
`undef MODULE
`undef MODULE
Line 170... Line 136...
      q <= ram[adr];
      q <= ram[adr];
 
 
endmodule
endmodule
`endif
`endif
 
 
// Dual port RAM
 
 
 
// ACTEL FPGA should not use logic to handle rw collision
 
`ifdef ACTEL
`ifdef ACTEL
 
        // ACTEL FPGA should not use logic to handle rw collision
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
        `define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`else
`else
        `define SYN
        `define SYN
`endif
`endif
 
 
Line 727... Line 691...
`undef MODULE
`undef MODULE
 
 
endmodule
endmodule
`endif
`endif
 
 
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`ifdef REG_FILE
 
`define MODULE reg_file
 
module `BASE`MODULE (
 
`undef MODULE
 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
 
);
 
parameter data_width = 32;
 
parameter addr_width = 5;
 
input [addr_width-1:0] a1, a2, a3;
 
input [data_width-1:0] wd3;
 
input we3;
 
output [data_width-1:0] rd1, rd2;
 
input clk;
 
 
 
`ifdef ACTEL
 
reg [data_width-1:0] wd3_reg;
 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
 
reg we3_reg;
 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] `SYN;
 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] `SYN;
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
 
else
 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
 
 
    always @ (negedge clk)
 
    if (we3_reg)
 
        ram1[a3_reg] <= wd3;
 
    always @ (posedge clk)
 
        a1_reg <= a1;
 
    assign rd1 = ram1[a1_reg];
 
 
 
    always @ (negedge clk)
 
    if (we3_reg)
 
        ram2[a3_reg] <= wd3;
 
    always @ (posedge clk)
 
        a2_reg <= a2;
 
    assign rd2 = ram2[a2_reg];
 
 
 
`else
 
 
 
`define MODULE dpram_1r1w
 
`BASE`MODULE
 
    # ( .data_width(data_width), .addr_width(addr_width))
 
    ram1 (
 
        .d_a(wd3),
 
        .adr_a(a3),
 
        .we_a(we3),
 
        .clk_a(clk),
 
        .q_b(rd1),
 
        .adr_b(a1),
 
        .clk_b(clk) );
 
 
 
`BASE`MODULE
 
    # ( .data_width(data_width), .addr_width(addr_width))
 
    ram2 (
 
        .d_a(wd3),
 
        .adr_a(a3),
 
        .we_a(we3),
 
        .clk_a(clk),
 
        .q_b(rd2),
 
        .adr_b(a2),
 
        .clk_b(clk) );
 
`undef MODULE
 
 
 
`endif
 
 
 
endmodule
 
`endif
 
 
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