URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 65 and 68

Rev 65	Rev 68
Line 103...	Line 103...
module `BASE`MODULE ( d, adr, be, we, q, clk);	module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE	`undef MODULE

`parameter data_width = 32;`	`parameter data_width = 32;`
`parameter addr_width = 8;`	`parameter addr_width = 8;`
	`parameter mem_size = 256;`
`input [(data_width-1):0] d;`	`input [(data_width-1):0] d;`
`input [(addr_width-1):0] adr;`	`input [(addr_width-1):0] adr;`
`input [(addr_width/4)-1:0] be;`	`input [(addr_width/4)-1:0] be;`
`input we;`	`input we;`
`output reg [(data_width-1):0] q;`	`output reg [(data_width-1):0] q;`
`input clk;`	`input clk;`

`//E2_ifdef SYSTEMVERILOG`	`//E2_ifdef SYSTEMVERILOG`
`logic [data_width/8-1:0][7:0] ram[0:1<<(addr_width-2)-1];// # words = 1 << address width`	`logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width`
`//E2_else`	`//E2_else`
`reg [data_width-1:0] ram [(1<<addr_width)-1:0];`	`reg [data_width-1:0] ram [mem_size-1:0];`
`//E2_endif`	`//E2_endif`

`parameter memory_init = 0;`	`parameter memory_init = 0;`
`parameter memory_file = "vl_ram.vmem";`	`parameter memory_file = "vl_ram.vmem";`
`generate if (memory_init) begin : init_mem`	`generate if (memory_init) begin : init_mem`