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`define MODULE ram_be
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`define MODULE ram_be
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module `BASE`MODULE ( d, adr, be, we, q, clk);
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module `BASE`MODULE ( d, adr, be, we, q, clk);
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`undef MODULE
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`undef MODULE
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 6;
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parameter mem_size = 256;
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parameter mem_size = 256;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
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input we;
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