URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 68 and 72

Rev 68	Rev 72
Line 102...	Line 102...
`define MODULE ram_be	`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);	module `BASE`MODULE ( d, adr, be, we, q, clk);
`undef MODULE	`undef MODULE

`parameter data_width = 32;`	`parameter data_width = 32;`
`parameter addr_width = 8;`	`parameter addr_width = 6;`
`parameter mem_size = 256;`	`parameter mem_size = 256;`
`input [(data_width-1):0] d;`	`input [(data_width-1):0] d;`
`input [(addr_width-1):0] adr;`	`input [(addr_width-1):0] adr;`
`input [(addr_width/4)-1:0] be;`	`input [(addr_width/4)-1:0] be;`
`input we;`	`input we;`