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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 75 and 77

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Rev 75 Rev 77
Line 316... Line 316...
   reg [(b_data_width-1):0]       q_b;
   reg [(b_data_width-1):0]       q_b;
 
 
generate
generate
if (a_data_width==32 & b_data_width==64) begin : inst32to64
if (a_data_width==32 & b_data_width==64) begin : inst32to64
 
 
    wire [63:0] temp;
    wire [63:0] tmp;
    `define MODULE dpram_2r2w
    `define MODULE dpram_2r2w
    `BASE`MODULE
    `BASE`MODULE
    # (.data_width(8), .addr_width(b_addr_width-3))
    # (.data_width(8), .addr_width(b_addr_width-3))
    ram0 (
    ram0 (
        .d_a(d_a[7:0]),
        .d_a(d_a[7:0]),

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