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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 86 and 90

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Line 100... Line 100...
endmodule
endmodule
`endif
`endif
 
 
`ifdef RAM_BE
`ifdef RAM_BE
`define MODULE ram_be
`define MODULE ram_be
module `BASE`MODULE ( d, adr, be, we, q, clk);
module `BASE`MODULE ( d, adr, be, re, we, q, clk);
`undef MODULE
`undef MODULE
 
 
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 6;
   parameter addr_width = 6;
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input [(data_width/8)-1:0]    be;
   input [(data_width/8)-1:0]    be;
 
   input                         re;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
 
 
Line 143... Line 144...
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
    end
 
    if (re)
    q <= ram[adr];
    q <= ram[adr];
end
end
 
 
//E2_else
//E2_else
 
 
Line 158... Line 160...
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   end
   endgenerate
   endgenerate
 
 
   always @ (posedge clk)
   always @ (posedge clk)
 
    if (re)
      q <= ram[adr];
      q <= ram[adr];
 
 
//E2_endif
//E2_endif
 
 
   // Function to access RAM (for use by Verilator).
   // Function to access RAM (for use by Verilator).
   function [31:0] get_mem;
   function [31:0] get_mem;
      // verilator public
      // verilator public
      input [aw-1:0]             addr;
      input [addr_width-1:0]             addr;
      get_mem = ram[addr];
      get_mem = ram[addr];
   endfunction // get_mem
   endfunction // get_mem
 
 
   // Function to write RAM (for use by Verilator).
   // Function to write RAM (for use by Verilator).
   function set_mem;
   function set_mem;
      // verilator public
      // verilator public
      input [aw-1:0]             addr;
      input [addr_width-1:0]             addr;
      input [dw-1:0]             data;
      input [data_width-1:0]             data;
      ram[addr] = data;
      ram[addr] = data;
   endfunction // set_mem
   endfunction // set_mem
 
 
endmodule
endmodule
`endif
`endif

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