| Line 100... |
Line 100... |
endmodule
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endmodule
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`endif
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`endif
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|
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`ifdef RAM_BE
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`ifdef RAM_BE
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`define MODULE ram_be
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`define MODULE ram_be
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module `BASE`MODULE ( d, adr, be, we, q, clk);
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module `BASE`MODULE ( d, adr, be, re, we, q, clk);
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`undef MODULE
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`undef MODULE
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|
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 6;
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parameter addr_width = 6;
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parameter mem_size = 1<<addr_width;
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parameter mem_size = 1<<addr_width;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(data_width/8)-1:0] be;
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input [(data_width/8)-1:0] be;
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input re;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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|
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| Line 143... |
Line 144... |
if(be[3]) ram[adr][3] <= d[31:24];
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if(be[3]) ram[adr][3] <= d[31:24];
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if(be[2]) ram[adr][2] <= d[23:16];
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if(be[2]) ram[adr][2] <= d[23:16];
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if(be[1]) ram[adr][1] <= d[15:8];
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if(be[1]) ram[adr][1] <= d[15:8];
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if(be[0]) ram[adr][0] <= d[7:0];
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if(be[0]) ram[adr][0] <= d[7:0];
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end
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end
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if (re)
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q <= ram[adr];
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q <= ram[adr];
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end
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end
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|
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//E2_else
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//E2_else
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| Line 158... |
Line 160... |
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endgenerate
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|
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always @ (posedge clk)
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always @ (posedge clk)
|
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if (re)
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q <= ram[adr];
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q <= ram[adr];
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|
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//E2_endif
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//E2_endif
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|
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// Function to access RAM (for use by Verilator).
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// Function to access RAM (for use by Verilator).
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function [31:0] get_mem;
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function [31:0] get_mem;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [addr_width-1:0] addr;
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get_mem = ram[addr];
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get_mem = ram[addr];
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endfunction // get_mem
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endfunction // get_mem
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|
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// Function to write RAM (for use by Verilator).
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// Function to write RAM (for use by Verilator).
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function set_mem;
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function set_mem;
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// verilator public
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// verilator public
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input [aw-1:0] addr;
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input [addr_width-1:0] addr;
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input [dw-1:0] data;
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input [data_width-1:0] data;
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ram[addr] = data;
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ram[addr] = data;
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endfunction // set_mem
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endfunction // set_mem
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|
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endmodule
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endmodule
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`endif
|
`endif
|
