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`endif
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`endif
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`ifdef DPRAM_BE_2R2W
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`ifdef DPRAM_BE_2R2W
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`define MODULE dpram_be_2r2w
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`define MODULE dpram_be_2r2w
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module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
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module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
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`undef MODULE
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`undef MODULE
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parameter a_data_width = 32;
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parameter a_data_width = 32;
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parameter a_addr_width = 8;
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parameter a_addr_width = 8;
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parameter b_data_width = 32;
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parameter b_data_width = a_data_width;
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localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
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localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
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parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
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parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
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input [(a_data_width-1):0] d_a;
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input [(a_data_width-1):0] d_a;
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input [(a_addr_width-1):0] adr_a;
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input [(a_addr_width-1):0] adr_a;
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input [(a_data_width/8-1):0] be_a;
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input [(a_data_width/8-1):0] be_a;
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input re_a;
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input we_a;
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input we_a;
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output reg [(a_data_width-1):0] q_a;
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output reg [(a_data_width-1):0] q_a;
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input [(b_data_width-1):0] d_b;
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input [(b_data_width-1):0] d_b;
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input [(b_addr_width-1):0] adr_b;
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input [(b_addr_width-1):0] adr_b;
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input re_b,we_b;
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input [(b_data_width/8-1):0] be_b;
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output [(b_data_width-1):0] q_b;
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input we_b;
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output reg [(b_data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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//E2_ifdef SYSTEMVERILOG
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//E2_ifdef SYSTEMVERILOG
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// use a multi-dimensional packed array
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// use a multi-dimensional packed array
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//to model individual bytes within the word
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//to model individual bytes within the word
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generate
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generate
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if (a_data_width==32 & b_data_width==32) begin : dpram_3232
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if (a_data_width==32 & b_data_width==32) begin : dpram_3232
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logic [3:0][7:0] ram [0:mem_size-1];
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logic [3:0][7:0] ram [0:mem_size-1];
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reg [a_addr_width-1:0] rd_adr_a;
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reg [b_addr_width-1:0] rd_adr_b;
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always_ff@(posedge clk_a)
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always_ff@(posedge clk_a)
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begin
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begin
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if(we_a) begin
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if(we_a) begin
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if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
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if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
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if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
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if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
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if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
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if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
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end
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end
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end
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end
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always@(posedge clk_a or posedge rst)
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always@(posedge clk_a)
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if (rst)
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q_a = ram[adr_a];
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rd_adr_a <= 0;
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else if (re_a)
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rd_adr_a <= adr_a;
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assign q_a = ram[rd_adr_a];
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always_ff@(posedge clk_b)
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always_ff@(posedge clk_b)
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if(we_b)
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begin
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ram[adr_b] <= d_b;
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if(we_b) begin
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if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
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always@(posedge clk_b or posedge rst)
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if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
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if (rst)
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if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
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rd_adr_b <= 0;
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if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
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else if (re_b)
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end
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rd_adr_b <= adr_b;
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end
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assign q_b = ram[rd_adr_b];
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always@(posedge clk_b)
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q_b = ram[adr_b];
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end
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end
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endgenerate
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endgenerate
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//E2_else
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//E2_else
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// This modules requires SystemVerilog
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//E2_endif
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//E2_endif
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endmodule
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endmodule
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`endif
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`endif
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`ifdef CAM
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`ifdef CAM
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