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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 91 and 92

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Line 310... Line 310...
`endif
`endif
 
 
 
 
`ifdef DPRAM_BE_2R2W
`ifdef DPRAM_BE_2R2W
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, re_a, we_a, clk_a, d_b, q_b, adr_b, re_b, we_b, clk_b );
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
`undef MODULE
 
 
   parameter a_data_width = 32;
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter a_addr_width = 8;
   parameter b_data_width = 32;
   parameter b_data_width = a_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
 
 
   input [(a_data_width-1):0]      d_a;
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_data_width/8-1):0]    be_a;
   input [(a_data_width/8-1):0]    be_a;
   input                           re_a;
 
   input                           we_a;
   input                           we_a;
   output reg [(a_data_width-1):0] q_a;
   output reg [(a_data_width-1):0] q_a;
   input [(b_data_width-1):0]       d_b;
   input [(b_data_width-1):0]       d_b;
   input [(b_addr_width-1):0]       adr_b;
   input [(b_addr_width-1):0]       adr_b;
   input                           re_b,we_b;
   input [(b_data_width/8-1):0]    be_b;
   output [(b_data_width-1):0]      q_b;
   input                           we_b;
 
   output reg [(b_data_width-1):0]          q_b;
   input                           clk_a, clk_b;
   input                           clk_a, clk_b;
 
 
//E2_ifdef SYSTEMVERILOG
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
// use a multi-dimensional packed array
//to model individual bytes within the word
//to model individual bytes within the word
 
 
generate
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
 
   logic [3:0][7:0] ram [0:mem_size-1];
   logic [3:0][7:0] ram [0:mem_size-1];
    reg [a_addr_width-1:0] rd_adr_a;
 
    reg [b_addr_width-1:0] rd_adr_b;
 
 
 
    always_ff@(posedge clk_a)
    always_ff@(posedge clk_a)
    begin
    begin
        if(we_a) begin
        if(we_a) begin
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
Line 352... Line 350...
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
        end
        end
    end
    end
 
 
    always@(posedge clk_a or posedge rst)
    always@(posedge clk_a)
    if (rst)
        q_a = ram[adr_a];
        rd_adr_a <= 0;
 
    else if (re_a)
 
        rd_adr_a <= adr_a;
 
 
 
    assign q_a = ram[rd_adr_a];
 
 
 
    always_ff@(posedge clk_b)
    always_ff@(posedge clk_b)
    if(we_b)
    begin
        ram[adr_b] <= d_b;
        if(we_b) begin
 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
    always@(posedge clk_b or posedge rst)
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
    if (rst)
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
        rd_adr_b <= 0;
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
    else if (re_b)
        end
        rd_adr_b <= adr_b;
    end
 
 
    assign q_b = ram[rd_adr_b];
    always@(posedge clk_b)
 
        q_b = ram[adr_b];
 
 
end
end
endgenerate
endgenerate
 
 
//E2_else
//E2_else
 
    // This modules requires SystemVerilog
//E2_endif
//E2_endif
endmodule
endmodule
`endif
`endif
 
 
`ifdef CAM
`ifdef CAM

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