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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Diff between revs 93 and 95

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Rev 93 Rev 95
Line 115... Line 115...
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
 
 
 
 
//E2_ifdef SYSTEMVERILOG
//E2_ifdef SYSTEMVERILOG
 
    // use a multi-dimensional packed array
 
    //t o model individual bytes within the word
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
//E2_else
//E2_else
    reg [data_width-1:0] ram [mem_size-1:0];
    reg [data_width-1:0] ram [mem_size-1:0];
    wire [data_width/8-1:0] cke;
    wire [data_width/8-1:0] cke;
//E2_endif
//E2_endif
Line 132... Line 134...
     end
     end
   end
   end
   endgenerate
   endgenerate
 
 
//E2_ifdef SYSTEMVERILOG
//E2_ifdef SYSTEMVERILOG
// use a multi-dimensional packed array
 
//to model individual bytes within the word
 
 
 
always_ff@(posedge clk)
always_ff@(posedge clk)
begin
begin
    if(we) begin // note: we should have a for statement to support any bus width
    if(we) begin
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[3]) ram[adr][3] <= d[31:24];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[2]) ram[adr][2] <= d[23:16];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[1]) ram[adr][1] <= d[15:8];
        if(be[0]) ram[adr][0] <= d[7:0];
        if(be[0]) ram[adr][0] <= d[7:0];
    end
    end
Line 317... Line 317...
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
module `BASE`MODULE ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
`undef MODULE
`undef MODULE
 
 
   parameter a_data_width = 32;
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter a_addr_width = 8;
   parameter b_data_width = a_data_width;
   parameter b_data_width = 64; //a_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
 
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
 
 
 
   parameter init = 0;
 
   parameter memory_file = "vl_ram.vmem";
 
 
   input [(a_data_width-1):0]      d_a;
   input [(a_data_width-1):0]      d_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_addr_width-1):0]       adr_a;
   input [(a_data_width/8-1):0]    be_a;
   input [(a_data_width/8-1):0]    be_a;
   input                           we_a;
   input                           we_a;
Line 340... Line 344...
//to model individual bytes within the word
//to model individual bytes within the word
 
 
generate
generate
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
 
 
   logic [3:0][7:0] ram [0:mem_size-1];
    logic [0:3][7:0] ram [0:mem_size-1];
 
 
 
    initial
 
        if (init)
 
            $readmemh(memory_file, ram);
 
 
    always_ff@(posedge clk_a)
    always_ff@(posedge clk_a)
    begin
    begin
        if(we_a) begin
        if(we_a) begin
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
Line 371... Line 379...
        q_b = ram[adr_b];
        q_b = ram[adr_b];
 
 
end
end
endgenerate
endgenerate
 
 
 
generate
 
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
 
 
 
    logic [0:7][7:0] ram [0:mem_size-1];
 
 
 
    initial
 
        if (init)
 
            $readmemh(memory_file, ram);
 
 
 
    always_ff@(posedge clk_a)
 
    begin
 
        if(we_a) begin
 
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
 
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
 
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
 
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
 
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
 
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
 
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
 
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
 
        end
 
    end
 
 
 
    always@(posedge clk_a)
 
        q_a = ram[adr_a];
 
 
 
    always_ff@(posedge clk_b)
 
    begin
 
        if(we_b) begin
 
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
 
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
 
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
 
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
 
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
 
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
 
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
 
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
 
        end
 
    end
 
 
 
    always@(posedge clk_b)
 
        q_b = ram[adr_b];
 
 
 
end
 
endgenerate
 
 
 
generate
 
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
 
logic [31:0] temp;
 
`define MODULE dpram_be_2r2w
 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
 
`undef MODULE
 
dpram6464 (
 
    .d_a(d_a),
 
    .q_a(q_a),
 
    .adr_a(adr_a),
 
    .be_a(be_a),
 
    .we_a(we_a),
 
    .clk_a(clk_a),
 
    .d_b({d_b,d_b}),
 
    .q_b(temp),
 
    .adr_b(adr_b),
 
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
 
    .we_b(we_b),
 
    .clk_b(clk_b)
 
);
 
 
 
always_comb
 
    if (adr_b[0])
 
        q_b = temp[31:16];
 
    else
 
        q_b = temp[15:0];
 
 
 
end
 
endgenerate
 
 
 
generate
 
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
 
logic [63:0] temp;
 
`define MODULE dpram_be_2r2w
 
`BASE`MODULE # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
 
`undef MODULE
 
dpram6464 (
 
    .d_a({d_a,d_a}),
 
    .q_a(temp),
 
    .adr_a(adr_a[a_addr_width-1:1]),
 
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
 
    .we_a(we_a),
 
    .clk_a(clk_a),
 
    .d_b(d_b),
 
    .q_b(q_b),
 
    .adr_b(adr_b),
 
    .be_b(be_b),
 
    .we_b(we_b),
 
    .clk_b(clk_b)
 
);
 
 
 
always_comb
 
    if (adr_a[0])
 
        q_a = temp[63:32];
 
    else
 
        q_a = temp[31:0];
 
 
 
end
 
endgenerate
 
 
//E2_else
//E2_else
    // This modules requires SystemVerilog
    // This modules requires SystemVerilog
//E2_endif
//E2_endif
endmodule
endmodule
`endif
`endif

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